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authorJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>2015-04-23 19:52:11 +0530
committerJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>2015-04-23 19:53:29 +0530
commit122d805fd4bd478bb83536348291d34ae648364b (patch)
tree997ff00471b090d17cd49c93404b45c37b0c3086 /README
parent9694b724421b88acf7d553a55e4a43fa4e25e7be (diff)
downloadtalos-obmc-uboot-122d805fd4bd478bb83536348291d34ae648364b.zip
talos-obmc-uboot-122d805fd4bd478bb83536348291d34ae648364b.tar.gz
Revert "spi: add config option to enable the WP pin function on st micron flashes"
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Note: Even un-reverting this patch couldn't works as expected, based on the latest testing from Heiko Schocher. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'README')
-rw-r--r--README11
1 files changed, 0 insertions, 11 deletions
diff --git a/README b/README
index fc1fd52..82224f7 100644
--- a/README
+++ b/README
@@ -3086,17 +3086,6 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
Currently Xilinx Zynq qspi supports these type of connections.
- CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
- enable the W#/Vpp signal to disable writing to the status
- register on ST MICRON flashes like the N25Q128.
- The status register write enable/disable bit, combined with
- the W#/VPP signal provides hardware data protection for the
- device as follows: When the enable/disable bit is set to 1,
- and the W#/VPP signal is driven LOW, the status register
- nonvolatile bits become read-only and the WRITE STATUS REGISTER
- operation will not execute. The only way to exit this
- hardware-protected mode is to drive W#/VPP HIGH.
-
- SystemACE Support:
CONFIG_SYSTEMACE
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