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| author | Kyle Moffett <Kyle.D.Moffett@boeing.com> | 2011-10-18 11:05:29 +0000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-10-28 00:37:01 +0200 |
| commit | ce5207e191c59b3135303fd03b98dd2ac3701ba2 (patch) | |
| tree | d9f5458d8dde3142031f21b76e6909a9cb328ca0 /README | |
| parent | 2326a94db10d9b6c0bf322c6536cafcac8e85522 (diff) | |
| download | talos-obmc-uboot-ce5207e191c59b3135303fd03b98dd2ac3701ba2.tar.gz talos-obmc-uboot-ce5207e191c59b3135303fd03b98dd2ac3701ba2.zip | |
e1000: Allow direct access to the E1000 SPI EEPROM device
As a part of the manufacturing process for some of our custom hardware,
we are programming the EEPROMs attached to our Intel 82571EB controllers
from software using U-Boot and Linux.
This code provides several conditionally-compiled features to assist in
our manufacturing process:
CONFIG_CMD_E1000:
This is a basic "e1000" command which allows querying the controller
and (if other config options are set) performing EEPROM programming.
In particular, with CONFIG_E1000_SPI this allows you to display a
hex-dump of the EEPROM, copy to/from main memory, and verify/update
the software checksum.
CONFIG_E1000_SPI_GENERIC:
Build a generic SPI driver providing the standard U-Boot SPI driver
interface. This allows commands such as "sspi" to access the bus
attached to the E1000 controller. Additionally, some E1000 chipsets
can support user data in a reserved space in the E1000 EEPROM which
could be used for U-Boot environment storage.
CONFIG_E1000_SPI:
The core SPI access code used by the above interfaces.
For example, the following commands allow you to program the EEPROM from
a USB device (assumes CONFIG_E1000_SPI and CONFIG_CMD_E1000 are enabled):
usb start
fatload usb 0 $loadaddr 82571EB_No_Mgmt_Discrete-LOM.bin
e1000 0 spi program $loadaddr 0 1024
e1000 0 spi checksum update
Please keep in mind that the Intel-provided .eep files are organized as
16-bit words. When converting them to binary form for programming you
must byteswap each 16-bit word so that it is in little-endian form.
This means that when reading and writing words to the SPI EEPROM, the
bit ordering for each word looks like this on the wire:
Time >>>
------------------------------------------------------------------
... [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8], ...
------------------------------------------------------------------
(MSB is 15, LSB is 0).
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 15 |
1 files changed, 14 insertions, 1 deletions
@@ -957,7 +957,20 @@ The following options need to be configured: - NETWORK Support (PCI): CONFIG_E1000 - Support for Intel 8254x gigabit chips. + Support for Intel 8254x/8257x gigabit chips. + + CONFIG_E1000_SPI + Utility code for direct access to the SPI bus on Intel 8257x. + This does not do anything useful unless you set at least one + of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC. + + CONFIG_E1000_SPI_GENERIC + Allow generic access to the SPI bus on the Intel 8257x, for + example with the "sspi" command. + + CONFIG_CMD_E1000 + Management command for E1000 devices. When used on devices + with SPI support you can reprogram the EEPROM from U-Boot. CONFIG_E1000_FALLBACK_MAC default MAC for empty EEPROM after production. |
