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authorStefan Roese <sr@denx.de>2014-11-07 13:50:29 +0100
committerMarek Vasut <marex@denx.de>2014-11-07 16:09:10 +0100
commitd2bb937db911b19ed38dd4e5a30b5bf4f2e5a951 (patch)
tree02edc8d669f5b5f14ce7bf78dff107c922d9c7ad
parent51c580c6c92c01884f520f4ffaeb6885ee8e666e (diff)
downloadtalos-obmc-uboot-d2bb937db911b19ed38dd4e5a30b5bf4f2e5a951.tar.gz
talos-obmc-uboot-d2bb937db911b19ed38dd4e5a30b5bf4f2e5a951.zip
arm: socfpga: Add DW master SPI clock to clock_manager.c
This function will be needed by the upcoming Designware master SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
-rw-r--r--arch/arm/cpu/armv7/socfpga/clock_manager.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index d869f47c88..fa3b93a257 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
return clock;
}
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ clock = cm_get_per_vco_clk_hz();
+
+ /* get the clock prior L4 SP divider (periph_base_clk) */
+ reg = readl(&clock_manager_base->per_pll.perbaseclk);
+ clock /= (reg + 1);
+
+ return clock;
+}
+
static void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
@@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void)
printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+ printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
}
int set_cpu_clk_info(void)
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