dm: x86: pci: Convert chromebook_link to use driver model for pci

Move chromebook_link over to driver model for PCI.

This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)

This does not really take advantage of driver model fully, but it does work.
Furture work will improve the code structure to remove many of the explicit
calls to init the board.

Signed-off-by: Simon Glass <sjg@chromium.org>

9 files changed, 62 insertions, 68 deletions

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 56b19e37bb..7b74282a0a 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <malloc.h>
@@ -86,7 +87,7 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
 	bd82x6x_pci_dev_enable_resources(dev);
 }
 
-int bd82x6x_init_pci_devices(void)
+static int bd82x6x_probe(struct udevice *dev)
 {
 	const void *blob = gd->fdt_blob;
 	struct pci_controller *hose;
@@ -144,3 +145,24 @@ int bd82x6x_init(void)
 
 	return 0;
 }
+
+static const struct udevice_id bd82x6x_ids[] = {
+	{ .compatible = "intel,bd82x6x" },
+	{ }
+};
+
+U_BOOT_DRIVER(bd82x6x_drv) = {
+	.name		= "bd82x6x",
+	.id		= UCLASS_PCH,
+	.of_match	= bd82x6x_ids,
+	.probe		= bd82x6x_probe,
+};
+
+/*
+ * TODO(sjg@chromium.org): Move this to arch/x86/lib or similar when other
+ * boards also use a PCH
+ */
+UCLASS_DRIVER(pch) = {
+	.id		= UCLASS_PCH,
+	.name		= "pch",
+};
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index e6ef4815a0..2639ec2413 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -12,6 +12,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <asm/cpu.h>
@@ -126,19 +127,20 @@ int arch_cpu_init_dm(void)
 {
 	const void *blob = gd->fdt_blob;
 	struct pci_controller *hose;
+	struct udevice *bus;
 	int node;
 	int ret;
 
-	post_code(POST_CPU_INIT);
-	timer_set_base(rdtsc());
-
-	ret = x86_cpu_init_f();
+	post_code(0x70);
+	ret = uclass_get_device(UCLASS_PCI, 0, &bus);
+	post_code(0x71);
 	if (ret)
 		return ret;
+	post_code(0x72);
+	hose = dev_get_uclass_priv(bus);
 
-	ret = pci_early_init_hose(&hose);
-	if (ret)
-		return ret;
+	/* TODO(sjg@chromium.org): Get rid of gd->hose */
+	gd->hose = hose;
 
 	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
 	if (node < 0)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 33b11a1799..c20e180329 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <rtc.h>
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index 7f62a86e32..5e90f30e08 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -10,63 +10,24 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <pci.h>
 #include <asm/pci.h>
+#include <asm/post.h>
 #include <asm/arch/bd82x6x.h>
 #include <asm/arch/pch.h>
 
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
-			      struct pci_config_table *table)
-{
-	u8 secondary;
-
-	hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
-	if (secondary != 0)
-		pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_ivybridge_config_table[] = {
-	/* vendor, device, class, bus, dev, func */
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
-		PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
-	{}
-};
-
-void board_pci_setup_hose(struct pci_controller *hose)
-{
-	hose->config_table = pci_ivybridge_config_table;
-	hose->first_busno = 0;
-	hose->last_busno = 0;
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		       CONFIG_PCI_MEM_BUS,
-		       CONFIG_PCI_MEM_PHYS,
-		       CONFIG_PCI_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		       CONFIG_PCI_IO_BUS,
-		       CONFIG_PCI_IO_PHYS,
-		       CONFIG_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	pci_set_region(hose->regions + 2,
-		       CONFIG_PCI_PREF_BUS,
-		       CONFIG_PCI_PREF_PHYS,
-		       CONFIG_PCI_PREF_SIZE,
-		       PCI_REGION_PREFETCH);
-
-	hose->region_count = 3;
-}
-
-int board_pci_pre_scan(struct pci_controller *hose)
+static int pci_ivybridge_probe(struct udevice *bus)
 {
+	struct pci_controller *hose = dev_get_uclass_priv(bus);
 	pci_dev_t dev;
 	u16 reg16;
 
+	if (!(gd->flags & GD_FLG_RELOC))
+		return 0;
+	post_code(0x50);
 	bd82x6x_init();
+	post_code(0x51);
 
 	reg16 = 0xff;
 	dev = PCH_DEV;
@@ -82,19 +43,25 @@ int board_pci_pre_scan(struct pci_controller *hose)
 	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 
 	pci_write_bar32(hose, dev, 0, 0xf0000000);
+	post_code(0x52);
 
 	return 0;
 }
 
-int board_pci_post_scan(struct pci_controller *hose)
-{
-	int ret;
+static const struct dm_pci_ops pci_ivybridge_ops = {
+	.read_config	= pci_x86_read_config,
+	.write_config	= pci_x86_write_config,
+};
 
-	ret = bd82x6x_init_pci_devices();
-	if (ret) {
-		printf("bd82x6x_init_pci_devices() failed: %d\n", ret);
-		return ret;
-	}
+static const struct udevice_id pci_ivybridge_ids[] = {
+	{ .compatible = "intel,pci-ivybridge" },
+	{ }
+};
 
-	return 0;
-}
+U_BOOT_DRIVER(pci_ivybridge_drv) = {
+	.name		= "pci_ivybridge",
+	.id		= UCLASS_PCI,
+	.of_match	= pci_ivybridge_ids,
+	.ops		= &pci_ivybridge_ops,
+	.probe		= pci_ivybridge_probe,
+};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index cdbdb6827e..0a845f2971 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -200,7 +200,8 @@
 		};
 
 		lpc {
-			compatible = "intel,lpc";
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,bd82x6x";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			gen-dec = <0x800 0xfc 0x900 0xfc>;
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index e1d9a9b7b2..5ae32f7883 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -12,7 +12,6 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_pci_init(pci_dev_t dev);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
-int bd82x6x_init_pci_devices(void);
 int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
 		   const void *blob, int node);
 int bd82x6x_init(void);
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 2f0c714e59..f3196fdd3a 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -9,3 +9,4 @@ CONFIG_SMM_TSEG_SIZE=0x800000
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_DM_PCI=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index cbde39ed89..0613cd64a9 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -9,3 +9,4 @@ CONFIG_SMM_TSEG_SIZE=0x800000
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_DM_PCI=y
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index fa7da8963c..9fcc1bbea5 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -67,7 +67,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
 	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
 	COMPAT(PARADE_PS8625, "parade,ps8625"),
-	COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
+	COMPAT(COMPAT_INTEL_LPC, "intel,bd82x6x"),
 	COMPAT(INTEL_MICROCODE, "intel,microcode"),
 	COMPAT(MEMORY_SPD, "memory-spd"),
 	COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),