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authorMasahiro Yamada <yamada.masahiro@socionext.com>2015-03-23 00:07:32 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2015-03-24 00:15:58 +0900
commita509161a21ef7584d614dc1530a2756dcfb217e0 (patch)
tree01a59554b7e9281d97896ccb0e4a766bbd88d8c6
parent62118b7b0183d29755a101a6a5b88dee11c5f94b (diff)
downloadtalos-obmc-uboot-a509161a21ef7584d614dc1530a2756dcfb217e0.tar.gz
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ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper
The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-rw-r--r--arch/arm/mach-uniphier/cache_uniphier.c17
-rw-r--r--arch/arm/mach-uniphier/late_lowlevel_init.S5
2 files changed, 5 insertions, 17 deletions
diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c
index 4bf01bce3e..c1e9164489 100644
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -122,23 +122,6 @@ void v7_outer_cache_disable(void)
void enable_caches(void)
{
- uint32_t reg;
-
- /*
- * UniPhier SoCs must use L2 cache for init stack pointer.
- * We disable L2 and L1 in this order.
- * If CONFIG_SYS_DCACHE_OFF is not defined,
- * caches are enabled again with a new page table.
- */
-
- /* L2 disable */
- v7_outer_cache_disable();
-
- /* L1 disable */
- reg = get_cr();
- reg &= ~(CR_C | CR_M);
- set_cr(reg);
-
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S
index 22be2a21da..1363364c80 100644
--- a/arch/arm/mach-uniphier/late_lowlevel_init.S
+++ b/arch/arm/mach-uniphier/late_lowlevel_init.S
@@ -6,7 +6,12 @@
*/
#include <linux/linkage.h>
+#include <mach/ssc-regs.h>
ENTRY(lowlevel_init)
+ ldr r1, = SSCC
+ ldr r0, [r1]
+ bic r0, r0, #SSCC_ON @ L2 disable
+ str r0, [r1]
mov pc, lr
ENDPROC(lowlevel_init)
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