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| author | Stephen Warren <swarren@nvidia.com> | 2016-03-22 09:45:36 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-03-29 09:57:57 -0700 |
| commit | 8f83759fac57cb25e23f6f75c001fe23aea47ee1 (patch) | |
| tree | 67e875a91022af1f4e6895bf474603a874bd33a2 | |
| parent | f3c2cab87878d2ecd5bd796ee940dff814aa3255 (diff) | |
| download | talos-obmc-uboot-8f83759fac57cb25e23f6f75c001fe23aea47ee1.tar.gz talos-obmc-uboot-8f83759fac57cb25e23f6f75c001fe23aea47ee1.zip | |
ARM: tegra210: set PLLE_PTS bit when enabling PLLE
This bit needs to be set for system suspend/resume to work. This setting
will be documented in an updated TRM at some time in the future.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra210/clock.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index df92bdce88..f0052e7934 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1104,6 +1104,7 @@ static int tegra_pllref_enable(void) #define PLLE_MISC_IDDQ_SWCTL (1 << 14) #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13) #define PLLE_MISC_LOCK (1 << 11) +#define PLLE_PTS (1 << 8) #define PLLE_MISC_KCP(x) (((x) & 0x3) << 6) #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) #define PLLE_MISC_KVCO (1 << 0) @@ -1157,6 +1158,7 @@ int tegra_plle_enable(void) writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value |= PLLE_PTS; value &= ~PLLE_MISC_KCP(3); value &= ~PLLE_MISC_VREG_CTRL(3); value &= ~PLLE_MISC_KVCO; |
