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authorDavid Thompson <dthompson@mellanox.com>2019-03-19 14:13:42 -0400
committerJoel Stanley <joel@jms.id.au>2019-04-04 15:32:32 +1030
commit81cb655c5b0613c7e49ff0896e8653285487a094 (patch)
treeda67172091ef0165e05096d3b11e176b74404958
parentfc8646ea8a4f24ff8267fa2eee0ee33327f1f36c (diff)
downloadtalos-obmc-uboot-81cb655c5b0613c7e49ff0896e8653285487a094.tar.gz
talos-obmc-uboot-81cb655c5b0613c7e49ff0896e8653285487a094.zip
aspeed/ast-scu.c: add ast_get_m_pll_clk() for AST_SOC_G5
This code change adds the AST_SOC_G5 version of ast_get_m_pll_clk(), which is relevant to AST1520, AST2500, and AST3200 devices. This change properly enables the AST_SOC_G5 logic in print_cpuinfo(), which can be turned on by defining CONFIG_DISPLAY_CPUINFO. Signed-off-by: David Thompson <dthompson@mellanox.com> Reviewed-by: Shravan Ramani <sramani@mellanox.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
-rw-r--r--arch/arm/include/asm/arch-aspeed/ast_scu.h1
-rw-r--r--arch/arm/mach-aspeed/ast-scu.c42
2 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-aspeed/ast_scu.h b/arch/arm/include/asm/arch-aspeed/ast_scu.h
index d248416432..dcbc6730d4 100644
--- a/arch/arm/include/asm/arch-aspeed/ast_scu.h
+++ b/arch/arm/include/asm/arch-aspeed/ast_scu.h
@@ -37,6 +37,7 @@ extern void ast_scu_get_who_init_dram(void);
extern u32 ast_get_clk_source(void);
extern u32 ast_get_h_pll_clk(void);
+extern u32 ast_get_m_pll_clk(void);
extern u32 ast_get_ahbclk(void);
extern u32 ast_scu_get_vga_memsize(void);
diff --git a/arch/arm/mach-aspeed/ast-scu.c b/arch/arm/mach-aspeed/ast-scu.c
index 0cc0d67b5d..12de9b8036 100644
--- a/arch/arm/mach-aspeed/ast-scu.c
+++ b/arch/arm/mach-aspeed/ast-scu.c
@@ -72,6 +72,12 @@ struct soc_id {
#define SOC_ID(str, rev) { .name = str, .rev_id = rev, }
+/*
+ * The values for the silicon revision IDs shown below are from
+ * the ASPEED Technology document "AST2500/AST2520 Integrated
+ * Remote Management Processor A2 Datasheet", v1.6, pp 373-374.
+ */
+
static struct soc_id soc_map_table[] = {
SOC_ID("AST1100/AST2050-A0", 0x00000200),
SOC_ID("AST1100/AST2050-A1", 0x00000201),
@@ -100,6 +106,10 @@ static struct soc_id soc_map_table[] = {
SOC_ID("AST2510-A1", 0x04010103),
SOC_ID("AST2520-A1", 0x04010203),
SOC_ID("AST2530-A1", 0x04010403),
+ SOC_ID("AST2500-A2", 0x04030303),
+ SOC_ID("AST2510-A2", 0x04030103),
+ SOC_ID("AST2520-A2", 0x04030203),
+ SOC_ID("AST2530-A2", 0x04030403),
};
void ast_scu_init_eth(u8 num)
@@ -235,6 +245,38 @@ u32 ast_get_h_pll_clk(void)
return clk;
}
+/*
+ * The source code for ast_get_m_pll_clk() is adapted from
+ * the file "arch/arm/mach-aspeed/ast-bmc-scu.c" contained
+ * in the bootloader portion of the ASPEED AST2500 SDK, v4.05
+ */
+
+u32 ast_get_m_pll_clk(void)
+{
+ u32 clk = 0;
+ u32 m_pll_set = ast_scu_read(AST_SCU_M_PLL);
+
+ if (m_pll_set & SCU_M_PLL_OFF)
+ return 0;
+
+ /* Programming */
+ clk = ast_get_clk_source();
+ if (m_pll_set & SCU_M_PLL_BYPASS) {
+ return clk;
+ } else {
+ /* P = SCU20[13:18]
+ * M = SCU20[5:12]
+ * N = SCU20[0:4]
+ * mpll = 24MHz * [(M+1) /(N+1)] / (P+1)
+ */
+ clk = ((clk * (SCU_M_PLL_GET_MNUM(m_pll_set) + 1)) /
+ (SCU_M_PLL_GET_NNUM(m_pll_set) + 1)) /
+ (SCU_M_PLL_GET_PDNUM(m_pll_set) + 1);
+ }
+ debug("m_pll = %d\n", clk);
+ return clk;
+}
+
u32 ast_get_ahbclk(void)
{
unsigned int axi_div, ahb_div, hpll;
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