Initial revision

3 files changed, 1800 insertions, 0 deletions

diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c
new file mode 100644
index 0000000000..81f820a8d4
--- /dev/null
+++ b/board/eltec/mhpc/mhpc.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2001
+ * ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * Board specific routines for the miniHiPerCam
+ *
+ * - initialisation (eeprom)
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <linux/ctype.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+#include <video_fb.h>
+
+/* imports from common/main.c */
+extern char console_buffer[CFG_CBSIZE];
+
+extern void eeprom_init  (void);
+extern int  eeprom_read  (unsigned dev_addr, unsigned offset,
+                          unsigned char *buffer, unsigned cnt);
+extern int  eeprom_write (unsigned dev_addr, unsigned offset,
+                          unsigned char *buffer, unsigned cnt);
+
+/* globals */
+void *video_hw_init(void);
+void video_set_lut (unsigned int index,     /* color number */
+                    unsigned char r,        /* red */
+                    unsigned char g,        /* green */
+                    unsigned char b         /* blue */
+                    );
+
+GraphicDevice gdev;
+
+/* locals */
+static void video_circle (char *center, int radius, int color, int pitch);
+static void video_test_image (void);
+static void video_default_lut (unsigned int clut_type);
+
+/* revision info foer MHPC EEPROM offset 480 */
+typedef struct  {
+    char    board[12];      /* 000 - Board Revision information */
+    char    sensor;         /* 012 - Sensor Type information */
+    char    serial[8];      /* 013 - Board serial number */
+    char    etheraddr[6];   /* 021 - Ethernet node addresse */
+    char    revision[2];    /* 027 - Revision code */
+    char    option[3];      /* 029 - resevered for options */
+} revinfo;
+
+/* ------------------------------------------------------------------------- */
+
+static const unsigned int sdram_table[] =
+{
+    /* read single beat cycle */
+    0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
+    0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
+
+    /* read burst cycle */
+    0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
+    0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
+    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+    /* write single beat cycle */
+    0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
+    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+    /* write burst cycle */
+    0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
+    0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
+    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+    /* periodic timer expired */
+    0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
+    0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
+    0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+    /* exception */
+    0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
+};
+
+/* ------------------------------------------------------------------------- */
+
+int board_pre_init (void)
+{
+    volatile immap_t  *im = (immap_t *)CFG_IMMR;
+    volatile cpm8xx_t *cp = &(im->im_cpm);
+    volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
+
+    /* reset the port A s.a. cpm-routines */
+    ip->iop_padat = 0x0000;
+    ip->iop_papar = 0x0000;
+    ip->iop_padir = 0x0800;
+    ip->iop_paodr = 0x0000;
+
+    /* reset the port B for digital and LCD output */
+    cp->cp_pbdat  = 0x0300;
+    cp->cp_pbpar  = 0x5001;
+    cp->cp_pbdir  = 0x5301;
+    cp->cp_pbodr  = 0x0000;
+
+    /* reset the port C configured for SMC1 serial port and aqc. control */
+    ip->iop_pcdat = 0x0800;
+    ip->iop_pcpar = 0x0000;
+    ip->iop_pcdir = 0x0e30;
+    ip->iop_pcso  = 0x0000;
+
+    /* Config port D for LCD output */
+    ip->iop_pdpar = 0x1fff;
+    ip->iop_pddir = 0x1fff;
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+    puts ("Board: ELTEC miniHiperCam\n");
+    return(0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r(void)
+{
+    revinfo  mhpcRevInfo;
+    char     nid[32];
+    char     *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
+                                    "OMNIVISON OV7110 b&w", NULL };
+    char     hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+                         0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
+    int      i;
+
+    /* check revision data */
+    eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char*)&mhpcRevInfo, 32);
+
+    if (strncmp((char *)&mhpcRevInfo.board[2], "MHPC", 4) != 0)
+    {
+    printf ("Enter revision number (0-9): %c  ", mhpcRevInfo.revision[0]);
+    if (0 != readline (NULL))
+    {
+        mhpcRevInfo.revision[0] = (char)toupper(console_buffer[0]);
+    }
+
+    printf ("Enter revision character (A-Z): %c  ", mhpcRevInfo.revision[1]);
+    if (1 == readline (NULL))
+    {
+        mhpcRevInfo.revision[1] = (char)toupper(console_buffer[0]);
+    }
+
+    printf("Enter board name (V-XXXX-XXXX): %s  ", (char *)&mhpcRevInfo.board);
+    if (11 == readline (NULL))
+    {
+        for (i=0; i<11; i++)
+        {
+            mhpcRevInfo.board[i] =  (char)toupper(console_buffer[i]);
+            mhpcRevInfo.board[11] = '\0';
+        }
+    }
+
+    printf("Supported sensor types:\n");
+    i=0;
+    do
+    {
+        printf("\n    \'%d\' : %s\n", i, mhpcSensorTypes[i]);
+    } while ( mhpcSensorTypes[++i] != NULL );
+
+    do
+    {
+        printf("\nEnter sensor number (0-255): %d  ", (int)mhpcRevInfo.sensor );
+        if (0 != readline (NULL))
+        {
+        mhpcRevInfo.sensor = (unsigned char)simple_strtoul(console_buffer, NULL, 10);
+        }
+    } while ( mhpcRevInfo.sensor >= i );
+
+    printf("Enter serial number: %s ", (char *)&mhpcRevInfo.serial );
+    if (6 == readline (NULL))
+    {
+        for (i=0; i<6; i++)
+        {
+        mhpcRevInfo.serial[i] = console_buffer[i];
+        }
+        mhpcRevInfo.serial[6] = '\0';
+    }
+
+    printf("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ",
+              mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+              mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+              mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]  );
+    if (12 == readline (NULL))
+    {
+        for (i=0; i<12; i+=2)
+        {
+        mhpcRevInfo.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
+                             hex[toupper(console_buffer[i+1])-'0']);
+        }
+    }
+
+    /* setup new revision data */
+    eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char*)&mhpcRevInfo, 32);
+    }
+
+    /* set environment */
+    sprintf( nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+                  mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+                  mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+                  mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+    setenv("ethaddr", nid);
+
+    /* print actual board identification */
+    printf("Ident: %s %s Ser %s Rev %c%c\n",
+            mhpcRevInfo.board, (mhpcRevInfo.sensor==0?"color":"b&w"),
+            (char *)&mhpcRevInfo.serial,
+            mhpcRevInfo.revision[0], mhpcRevInfo.revision[1]);
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+    memctl->memc_mamr  = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+    memctl->memc_mbmr  = MAMR_GPL_B4DIS;
+    memctl->memc_mptpr = MPTPR_PTP_DIV64;
+    memctl->memc_mar   = 0x00008800;
+
+    /*
+     * Map controller SDRAM bank 0
+     */
+    memctl->memc_or1 = CFG_OR1_PRELIM;
+    memctl->memc_br1 = CFG_BR1_PRELIM;
+    udelay(200);
+
+    /*
+     * Map controller SDRAM bank 1
+     */
+    memctl->memc_or2 = CFG_OR2;
+    memctl->memc_br2 = CFG_BR2;
+
+    /*
+     * Perform SDRAM initializsation sequence
+     */
+    memctl->memc_mcr  = 0x80002105;    /* SDRAM bank 0 */
+    udelay(1);
+    memctl->memc_mcr  = 0x80002730;    /* SDRAM bank 0 - execute twice */
+    udelay(1);
+    memctl->memc_mamr |= MAMR_PTAE;    /* enable refresh */
+
+    udelay(10000);
+
+    /* leave place for framebuffers */
+    return (SDRAM_MAX_SIZE-SDRAM_RES_SIZE);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_circle (char *center, int radius, int color, int pitch)
+{
+    int x,y,d,dE,dSE;
+
+    x   = 0;
+    y   = radius;
+    d   = 1-radius;
+    dE  = 3;
+    dSE = -2*radius+5;
+
+    *(center+x+y*pitch) = color;
+    *(center+y+x*pitch) = color;
+    *(center+y-x*pitch) = color;
+    *(center+x-y*pitch) = color;
+    *(center-x-y*pitch) = color;
+    *(center-y-x*pitch) = color;
+    *(center-y+x*pitch) = color;
+    *(center-x+y*pitch) = color;
+    while(y>x)
+    {
+        if (d<0)
+        {
+            d   += dE;
+            dE  += 2;
+            dSE += 2;
+            x++;
+        }
+        else
+        {
+            d   += dSE;
+            dE  += 2;
+            dSE += 4;
+            x++;
+            y--;
+        }
+        *(center+x+y*pitch) = color;
+        *(center+y+x*pitch) = color;
+        *(center+y-x*pitch) = color;
+        *(center+x-y*pitch) = color;
+        *(center-x-y*pitch) = color;
+        *(center-y-x*pitch) = color;
+        *(center-y+x*pitch) = color;
+        *(center-x+y*pitch) = color;
+    }
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_test_image(void)
+{
+    char *di;
+    int i, n;
+
+    /* draw raster */
+    for (i=0; i<LCD_VIDEO_ROWS; i+=32)
+    {
+        memset((char*)(LCD_VIDEO_ADDR+i*LCD_VIDEO_COLS), LCD_VIDEO_FG, LCD_VIDEO_COLS);
+        for (n=i+1;n<i+32;n++)
+            memset((char*)(LCD_VIDEO_ADDR+n*LCD_VIDEO_COLS), LCD_VIDEO_BG, LCD_VIDEO_COLS);
+    }
+
+    for (i=0; i<LCD_VIDEO_COLS; i+=32)
+    {
+        for (n=0; n<LCD_VIDEO_ROWS; n++)
+            *(char*)(LCD_VIDEO_ADDR+n*LCD_VIDEO_COLS+i) = LCD_VIDEO_FG;
+    }
+
+    /* draw gray bar */
+    di = (char *)(LCD_VIDEO_ADDR + (LCD_VIDEO_COLS-256)/64*32 + 97*LCD_VIDEO_COLS);
+    for (n=0; n<63; n++)
+    {
+        for (i=0; i<256; i++)
+        {
+            *di++ = (char)i;
+            *(di+LCD_VIDEO_COLS*64) = (i&1)*255;
+        }
+        di += LCD_VIDEO_COLS-256;
+    }
+
+    video_circle ((char*)LCD_VIDEO_ADDR+LCD_VIDEO_COLS/2+LCD_VIDEO_ROWS/2*LCD_VIDEO_COLS,
+                  LCD_VIDEO_ROWS/2,LCD_VIDEO_FG, LCD_VIDEO_COLS);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_default_lut (unsigned int clut_type)
+{
+    unsigned int i;
+    unsigned char RGB[] =
+        {
+        0x00, 0x00, 0x00,   /* black */
+        0x80, 0x80, 0x80,   /* gray */
+        0xff, 0x00, 0x00,   /* red */
+        0x00, 0xff, 0x00,   /* green */
+        0x00, 0x00, 0xff,   /* blue */
+        0x00, 0xff, 0xff,   /* cyan */
+        0xff, 0x00, 0xff,   /* magenta */
+        0xff, 0xff, 0x00,   /* yellow */
+        0x80, 0x00, 0x00,   /* dark red */
+        0x00, 0x80, 0x00,   /* dark green */
+        0x00, 0x00, 0x80,   /* dark blue */
+        0x00, 0x80, 0x80,   /* dark cyan */
+        0x80, 0x00, 0x80,   /* dark magenta */
+        0x80, 0x80, 0x00,   /* dark yellow */
+        0xc0, 0xc0, 0xc0,   /* light gray */
+        0xff, 0xff, 0xff,   /* white */
+        };
+
+    switch (clut_type)
+    {
+    case 1:
+        for (i=0; i<240; i++)
+            video_set_lut (i, i, i, i);
+        for (i=0; i<16; i++)
+            video_set_lut (i+240, RGB[i*3], RGB[i*3+1], RGB[i*3+2]);
+        break;
+    default:
+        for (i=0; i<256; i++)
+            video_set_lut (i, i, i, i);
+    }
+}
+
+/* ------------------------------------------------------------------------- */
+
+void *video_hw_init (void)
+{
+    unsigned int clut = 0;
+    unsigned char *penv;
+    immap_t *immr = (immap_t *) CFG_IMMR;
+
+    /* enable video only on CLUT value */
+    if ((penv = getenv ("clut")) != NULL)
+        clut = (u_int)simple_strtoul (penv, NULL, 10);
+    else
+        return NULL;
+
+    /* disable graphic before write LCD regs. */
+    immr->im_lcd.lcd_lccr = 0x96000866;
+
+    /* config LCD regs. */
+    immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
+    immr->im_lcd.lcd_lchcr = 0x010a0093;
+    immr->im_lcd.lcd_lcvcr = 0x900f0024;
+
+    printf ("Video: 640x480 8Bit Index Lut %s\n",
+            (clut==1?"240/16 (gray/vga)":"256(gray)"));
+
+    video_default_lut (clut);
+
+    /* clear framebuffer */
+    memset ( (char*)(LCD_VIDEO_ADDR), LCD_VIDEO_BG, LCD_VIDEO_ROWS*LCD_VIDEO_COLS );
+
+    /* enable graphic */
+    immr->im_lcd.lcd_lccr = 0x96000867;
+
+    /* fill in Graphic Device */
+    gdev.frameAdrs = LCD_VIDEO_ADDR;
+    gdev.winSizeX = LCD_VIDEO_COLS;
+    gdev.winSizeY = LCD_VIDEO_ROWS;
+    gdev.gdfBytesPP = 1;
+    gdev.gdfIndex = GDF__8BIT_INDEX;
+
+    if (clut > 1)
+        /* return Graphic Device for console */
+        return (void *)&gdev;
+    else
+        /* just graphic enabled - draw something beautiful */
+        video_test_image();
+
+    return NULL;            /* this disabels cfb - console */
+}
+
+/* ------------------------------------------------------------------------- */
+
+void video_set_lut (unsigned int index,
+                    unsigned char r, unsigned char g, unsigned char b)
+{
+    unsigned int lum;
+    unsigned short *pLut = (unsigned short *)(CFG_IMMR + 0x0e00);
+
+    /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
+    /* y = 0.299*R + 0.587*G + 0.114*B */
+    lum = (2990*r + 5870*g + 1140*b)/10000;
+    pLut[index] = ((b & 0xc0)<<4) | ((g & 0xc0)<<2) | (r & 0xc0) | (lum & 0x3f);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
new file mode 100644
index 0000000000..87ca6ef4be
--- /dev/null
+++ b/board/mpl/pip405/pip405.c
@@ -0,0 +1,947 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * TODO: clean-up
+ */
+
+#include <common.h>
+#include "pip405.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include "../common/isa.h"
+#include "../common/common_util.h"
+
+#undef SDRAM_DEBUG
+
+#define FALSE           0
+#define TRUE            1
+
+/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
+#ifndef __ldiv_t_defined
+typedef struct {
+	long int quot;		/* Quotient */
+	long int rem;		/* Remainder    */
+} ldiv_t;
+extern ldiv_t ldiv (long int __numer, long int __denom);
+
+# define __ldiv_t_defined	1
+#endif
+
+
+typedef enum {
+	SDRAM_NO_ERR,
+	SDRAM_SPD_COMM_ERR,
+	SDRAM_SPD_CHKSUM_ERR,
+	SDRAM_UNSUPPORTED_ERR,
+	SDRAM_UNKNOWN_ERR
+} SDRAM_ERR;
+
+typedef struct {
+	const unsigned char mode;
+	const unsigned char row;
+	const unsigned char col;
+	const unsigned char bank;
+} SDRAM_SETUP;
+
+static const SDRAM_SETUP sdram_setup_table[] = {
+	{1, 11, 9, 2},
+	{1, 11, 10, 2},
+	{2, 12, 9, 4},
+	{2, 12, 10, 4},
+	{3, 13, 9, 4},
+	{3, 13, 10, 4},
+	{3, 13, 11, 4},
+	{4, 12, 8, 2},
+	{4, 12, 8, 4},
+	{5, 11, 8, 2},
+	{5, 11, 8, 4},
+	{6, 13, 8, 2},
+	{6, 13, 8, 4},
+	{7, 13, 9, 2},
+	{7, 13, 10, 2},
+	{0, 0, 0, 0}
+};
+
+static const unsigned char cal_indextable[] = {
+	9, 23, 25
+};
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns.ns/4 coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
+{
+	unsigned short ns, ns4;
+
+	/* isolate upper 6 bits */
+	ns = (spd_byte >> 2) & 0x3F;
+	/* isloate lower 2 bits */
+	ns4 = (spd_byte & 0x03);
+
+	return (ns * 100 + ns4 * 25);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+void SDRAM_err (const char *s)
+{
+#ifndef SDRAM_DEBUG
+	DECLARE_GLOBAL_DATA_PTR;
+
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+#endif
+	serial_puts ("\n");
+	serial_puts (s);
+	serial_puts ("\n enable SDRAM_DEBUG for more info\n");
+	for (;;);
+}
+
+
+#ifdef SDRAM_DEBUG
+
+void write_hex (unsigned char i)
+{
+	char cc;
+
+	cc = i >> 4;
+	cc &= 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+	cc = i & 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+}
+
+void write_4hex (unsigned long val)
+{
+	write_hex ((unsigned char) (val >> 24));
+	write_hex ((unsigned char) (val >> 16));
+	write_hex ((unsigned char) (val >> 8));
+	write_hex ((unsigned char) val);
+}
+
+#endif
+
+int board_pre_init (void)
+{
+	unsigned char dataout[1];
+	unsigned char datain[128];
+	unsigned long sdram_size;
+	SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
+	unsigned long memclk;
+	unsigned long tmemclk = 0;
+	unsigned long tmp, bank, baseaddr, bank_size;
+	unsigned short i;
+	unsigned char rows, cols, banks, sdram_banks, density;
+	unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
+			trc_clocks, tctp_clocks;
+	unsigned char cal_index, cal_val, spd_version, spd_chksum;
+	unsigned char buf[8];
+#ifdef SDRAM_DEBUG
+	DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+	memclk = get_bus_freq (tmemclk);
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+#ifdef SDRAM_DEBUG
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+	serial_puts ("\nstart SDRAM Setup\n");
+#endif
+
+	/* Read Serial Presence Detect Information */
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	dataout[0] = 0;
+	for (i = 0; i < 128; i++)
+		datain[i] = 127;
+	i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
+#ifdef SDRAM_DEBUG
+	serial_puts ("\ni2c_read returns ");
+	write_hex (i);
+	serial_puts ("\n");
+#endif
+
+#ifdef SDRAM_DEBUG
+	for (i = 0; i < 128; i++) {
+		write_hex (datain[i]);
+		serial_puts (" ");
+		if (((i + 1) % 16) == 0)
+			serial_puts ("\n");
+	}
+	serial_puts ("\n");
+#endif
+	spd_chksum = 0;
+	for (i = 0; i < 63; i++) {
+		spd_chksum += datain[i];
+	}							/* endfor */
+	if (datain[63] != spd_chksum) {
+#ifdef SDRAM_DEBUG
+		serial_puts ("SPD chksum: 0x");
+		write_hex (datain[63]);
+		serial_puts (" != calc. chksum: 0x");
+		write_hex (spd_chksum);
+		serial_puts ("\n");
+#endif
+		SDRAM_err ("SPD checksum Error");
+	}
+	/* SPD seems to be ok, use it */
+
+	/* get SPD version */
+	spd_version = datain[62];
+
+	/* do some sanity checks on the kind of RAM */
+	if ((datain[0] < 0x80) ||	/* less than 128 valid bytes in SPD */
+		(datain[2] != 0x04) ||	/* if not SDRAM */
+		(!((datain[6] == 0x40) || (datain[6] == 0x48))) ||	/* or not (64 Bit or 72 Bit)  */
+		(datain[7] != 0x00) || (datain[8] != 0x01) ||	/* or not LVTTL signal levels */
+		(datain[126] == 0x66))	/* or a 66Mhz modules */
+		SDRAM_err ("unsupported SDRAM");
+#ifdef SDRAM_DEBUG
+	serial_puts ("SDRAM sanity ok\n");
+#endif
+
+	/* get number of rows/cols/banks out of byte 3+4+5 */
+	rows = datain[3];
+	cols = datain[4];
+	banks = datain[5];
+
+	/* get number of SDRAM banks out of byte 17 and
+	   supported CAS latencies out of byte 18 */
+	sdram_banks = datain[17];
+	supported_cal = datain[18] & ~0x81;
+
+	while (t->mode != 0) {
+		if ((t->row == rows) && (t->col == cols)
+			&& (t->bank == sdram_banks))
+			break;
+		t++;
+	}							/* endwhile */
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("rows: ");
+	write_hex (rows);
+	serial_puts (" cols: ");
+	write_hex (cols);
+	serial_puts (" banks: ");
+	write_hex (banks);
+	serial_puts (" mode: ");
+	write_hex (t->mode);
+	serial_puts ("\n");
+#endif
+	if (t->mode == 0)
+		SDRAM_err ("unsupported SDRAM");
+	/* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
+#ifdef SDRAM_DEBUG
+	serial_puts ("tRP: ");
+	write_hex (datain[27]);
+	serial_puts ("\ntRCD: ");
+	write_hex (datain[29]);
+	serial_puts ("\ntRAS: ");
+	write_hex (datain[30]);
+	serial_puts ("\n");
+#endif
+
+	trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
+	trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
+	tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
+	density = datain[31];
+
+	/* trc_clocks is sum of trp_clocks + tras_clocks */
+	trc_clocks = trp_clocks + tras_clocks;
+	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
+	tctp_clocks =
+			((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
+			 (tmemclk - 1)) / tmemclk;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("c_RP: ");
+	write_hex (trp_clocks);
+	serial_puts ("\nc_RCD: ");
+	write_hex (trcd_clocks);
+	serial_puts ("\nc_RAS: ");
+	write_hex (tras_clocks);
+	serial_puts ("\nc_RC: (RP+RAS): ");
+	write_hex (trc_clocks);
+	serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
+	write_hex (tctp_clocks);
+	serial_puts ("\nt_CTP: RAS - RCD: ");
+	write_hex ((unsigned
+				char) ((NSto10PS (datain[30]) -
+						NSto10PS (datain[29])) >> 8));
+	write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
+	serial_puts ("\ntmemclk: ");
+	write_hex ((unsigned char) (tmemclk >> 8));
+	write_hex ((unsigned char) (tmemclk));
+	serial_puts ("\n");
+#endif
+
+
+	cal_val = 255;
+	for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
+		/* is this CAS latency supported ? */
+		if ((supported_cal >> i) & 0x01) {
+			buf[0] = datain[cal_indextable[cal_index]];
+			if (cal_index < 2) {
+				if (NS10to10PS (buf[0], spd_version) <= tmemclk)
+					cal_val = i;
+			} else {
+				/* SPD bytes 25+26 have another format */
+				if (NS4to10PS (buf[0], spd_version) <= tmemclk)
+					cal_val = i;
+			}	/* endif */
+			cal_index++;
+		}	/* endif */
+	}	/* endfor */
+#ifdef SDRAM_DEBUG
+	serial_puts ("CAL: ");
+	write_hex (cal_val + 1);
+	serial_puts ("\n");
+#endif
+
+	if (cal_val == 255)
+		SDRAM_err ("unsupported SDRAM");
+
+	/* get SDRAM timing register */
+	mtdcr (memcfga, mem_sdtr1);
+	tmp = mfdcr (memcfgd) & ~0x018FC01F;
+	/* insert CASL value */
+/*  tmp |= ((unsigned long)cal_val) << 23; */
+	tmp |= ((unsigned long) cal_val) << 23;
+	/* insert PTA value */
+	tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
+	/* insert CTP value */
+/*  tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
+	tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
+	/* insert LDF (always 01) */
+	tmp |= ((unsigned long) 0x01) << 14;
+	/* insert RFTA value */
+	tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
+	/* insert RCD value */
+	tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("sdtr: ");
+	write_4hex (tmp);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM timing register */
+	mtdcr (memcfga, mem_sdtr1);
+	mtdcr (memcfgd, tmp);
+	baseaddr = CFG_SDRAM_BASE;
+	bank_size = (((unsigned long) density) << 22) / 2;
+	/* insert AM value */
+	tmp = ((unsigned long) t->mode - 1) << 13;
+	/* insert SZ value; */
+	switch (bank_size) {
+	case 0x00400000:
+		tmp |= ((unsigned long) 0x00) << 17;
+		break;
+	case 0x00800000:
+		tmp |= ((unsigned long) 0x01) << 17;
+		break;
+	case 0x01000000:
+		tmp |= ((unsigned long) 0x02) << 17;
+		break;
+	case 0x02000000:
+		tmp |= ((unsigned long) 0x03) << 17;
+		break;
+	case 0x04000000:
+		tmp |= ((unsigned long) 0x04) << 17;
+		break;
+	case 0x08000000:
+		tmp |= ((unsigned long) 0x05) << 17;
+		break;
+	case 0x10000000:
+		tmp |= ((unsigned long) 0x06) << 17;
+		break;
+	default:
+		SDRAM_err ("unsupported SDRAM");
+	}	/* endswitch */
+	/* get SDRAM bank 0 register */
+	mtdcr (memcfga, mem_mb0cf);
+	bank = mfdcr (memcfgd) & ~0xFFCEE001;
+	bank |= (baseaddr | tmp | 0x01);
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank0: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+	serial_puts (" mb0cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+	baseaddr += bank_size;
+	sdram_size += bank_size;
+
+	/* write SDRAM bank 0 register */
+	mtdcr (memcfga, mem_mb0cf);
+	mtdcr (memcfgd, bank);
+
+	/* get SDRAM bank 1 register */
+	mtdcr (memcfga, mem_mb1cf);
+	bank = mfdcr (memcfgd) & ~0xFFCEE001;
+	sdram_size = 0;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank1: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+#endif
+	if (banks == 2) {
+		bank |= (baseaddr | tmp | 0x01);
+		baseaddr += bank_size;
+		sdram_size += bank_size;
+	}	/* endif */
+#ifdef SDRAM_DEBUG
+	serial_puts (" mb1cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+	/* write SDRAM bank 1 register */
+	mtdcr (memcfga, mem_mb1cf);
+	mtdcr (memcfgd, bank);
+
+	/* get SDRAM bank 2 register */
+	mtdcr (memcfga, mem_mb2cf);
+	bank = mfdcr (memcfgd) & ~0xFFCEE001;
+
+	bank |= (baseaddr | tmp | 0x01);
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank2: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+	serial_puts (" mb2cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+
+	baseaddr += bank_size;
+	sdram_size += bank_size;
+
+	/* write SDRAM bank 2 register */
+	mtdcr (memcfga, mem_mb2cf);
+	mtdcr (memcfgd, bank);
+
+	/* get SDRAM bank 3 register */
+	mtdcr (memcfga, mem_mb3cf);
+	bank = mfdcr (memcfgd) & ~0xFFCEE001;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank3: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+#endif
+
+	if (banks == 2) {
+		bank |= (baseaddr | tmp | 0x01);
+		baseaddr += bank_size;
+		sdram_size += bank_size;
+	}
+	/* endif */
+#ifdef SDRAM_DEBUG
+	serial_puts (" mb3cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM bank 3 register */
+	mtdcr (memcfga, mem_mb3cf);
+	mtdcr (memcfgd, bank);
+
+
+	/* get SDRAM refresh interval register */
+	mtdcr (memcfga, mem_rtr);
+	tmp = mfdcr (memcfgd) & ~0x3FF80000;
+
+	if (tmemclk < NSto10PS (16))
+		tmp |= 0x05F00000;
+	else
+		tmp |= 0x03F80000;
+
+	/* write SDRAM refresh interval register */
+	mtdcr (memcfga, mem_rtr);
+	mtdcr (memcfgd, tmp);
+
+	/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
+	mtdcr (memcfga, mem_mcopt1);
+	tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
+	mtdcr (memcfga, mem_mcopt1);
+	mtdcr (memcfgd, tmp);
+
+
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the PIP405 board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for PIP405 board:
+   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
+   |       the Interrupt Controller in the South Bridge has caused the
+   |       interrupt. The IC must be read to determine which device
+   |       caused the interrupt.
+   |
+   +-------------------------------------------------------------------------*/
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */
+	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char s[50];
+	unsigned char bc;
+	int i;
+	backup_t *b = (backup_t *) s;
+
+	puts ("Board: ");
+
+	i = getenv_r ("serial#", s, 32);
+	if ((i == 0) || strncmp (s, "PIP405", 6)) {
+		get_backup_values (b);
+		if (strncmp (b->signature, "MPL\0", 4) != 0) {
+			puts ("### No HW ID - assuming PIP405");
+		} else {
+			b->serial_name[6] = 0;
+			printf ("%s SN: %s", b->serial_name,
+				&b->serial_name[7]);
+		}
+	} else {
+		s[6] = 0;
+		printf ("%s SN: %s", s, &s[7]);
+	}
+	bc = in8 (CONFIG_PORT_ADDR);
+	printf (" Boot Config: 0x%x\n", bc);
+	return (0);
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/*
+  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  the necessary info for SDRAM controller configuration
+*/
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+static int test_dram (unsigned long ramsize);
+
+long int initdram (int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned long bank_reg[4], tmp, bank_size;
+	int i, ds;
+	unsigned long TotalSize;
+
+	ds = 0;
+	/* since the DRAM controller is allready set up,
+	 * calculate the size with the bank registers
+	 */
+	mtdcr (memcfga, mem_mb0cf);
+	bank_reg[0] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb1cf);
+	bank_reg[1] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb2cf);
+	bank_reg[2] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb3cf);
+	bank_reg[3] = mfdcr (memcfgd);
+	TotalSize = 0;
+	for (i = 0; i < 4; i++) {
+		if ((bank_reg[i] & 0x1) == 0x1) {
+			tmp = (bank_reg[i] >> 17) & 0x7;
+			bank_size = 4 << tmp;
+			TotalSize += bank_size;
+		} else
+			ds = 1;
+	}
+	if (ds == 1)
+		printf ("single-sided DIMM ");
+	else
+		printf ("double-sided DIMM ");
+	test_dram (TotalSize * 1024 * 1024);
+	/* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
+	(void) get_clocks();
+	if (gd->cpu_clk > 220000000)
+		TotalSize /= 2;
+	return (TotalSize * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static int test_dram (unsigned long ramsize)
+{
+	/* not yet implemented */
+	return (1);
+}
+
+
+int misc_init_r (void)
+{
+	return (0);
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+
+int overwrite_console (void)
+{
+	return (in8 (CONFIG_PORT_ADDR) & 0x1);	/* return TRUE if console should be overwritten */
+}
+
+
+
+extern int isa_init (void);
+
+
+void print_pip405_rev (void)
+{
+	unsigned char part, vers, cfg;
+
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	cfg = in8 (PLD_BOARD_CFG_REG);
+	printf ("Rev:   PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
+			16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
+			vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
+}
+
+extern void check_env(void);
+
+
+int last_stage_init (void)
+{
+	print_pip405_rev ();
+	isa_init ();
+	show_stdio_dev ();
+	check_env();
+	return 0;
+}
+
+/************************************************************************
+* Print PIP405 Info
+************************************************************************/
+void print_pip405_info (void)
+{
+	unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
+			compwr, nicvga, scsirst;
+
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	cfg = in8 (PLD_BOARD_CFG_REG);
+	ledu = in8 (PLD_LED_USER_REG);
+	sysman = in8 (PLD_SYS_MAN_REG);
+	flashcom = in8 (PLD_FLASH_COM_REG);
+	can = in8 (PLD_CAN_REG);
+	serpwr = in8 (PLD_SER_PWR_REG);
+	compwr = in8 (PLD_COM_PWR_REG);
+	nicvga = in8 (PLD_NIC_VGA_REG);
+	scsirst = in8 (PLD_SCSI_RST_REG);
+	printf ("PLD Part %d version %d\n",
+		part & 0xf, vers & 0xf);
+	printf ("PLD Part %d version %d\n",
+		(part >> 4) & 0xf, (vers >> 4) & 0xf);
+	printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
+	printf ("Population Options %d %d %d %d\n",
+		(cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
+		(cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
+	printf ("User LED0 %s User LED1 %s\n",
+		((ledu & 0x1) == 0x1) ? "on" : "off",
+		((ledu & 0x2) == 0x2) ? "on" : "off");
+	printf ("Additionally Options %d %d\n",
+		(ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
+	printf ("User Config Switch %d %d %d %d\n",
+		(ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
+		(ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
+	switch (sysman & 0x3) {
+	case 0:
+		printf ("PCI Clocks are running\n");
+		break;
+	case 1:
+		printf ("PCI Clocks are stopped in POS State\n");
+		break;
+	case 2:
+		printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
+		break;
+	case 3:
+		printf ("PCI Clocks are stopped\n");
+		break;
+	}
+	switch ((sysman >> 2) & 0x3) {
+	case 0:
+		printf ("Main Clocks are running\n");
+		break;
+	case 1:
+		printf ("Main Clocks are stopped in POS State\n");
+		break;
+	case 2:
+	case 3:
+		printf ("PCI Clocks are stopped\n");
+		break;
+	}
+	printf ("INIT asserts %sINT2# (SMI)\n",
+			((sysman & 0x10) == 0x10) ? "" : "not ");
+	printf ("INIT asserts %sINT1# (NMI)\n",
+			((sysman & 0x20) == 0x20) ? "" : "not ");
+	printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
+	printf ("SER1 is routed to %s\n",
+			((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
+	printf ("COM2 is routed to %s\n",
+			((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
+	printf ("RS485 is configured as %s duplex\n",
+			((flashcom & 0x4) == 0x4) ? "full" : "half");
+	printf ("RS485 is connected to %s\n",
+			((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
+	printf ("SER1 uses handshakes %s\n",
+			((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
+	printf ("Bootflash is %swriteprotected\n",
+			((flashcom & 0x20) == 0x20) ? "not " : "");
+	printf ("Bootflash VPP is %s\n",
+			((flashcom & 0x40) == 0x40) ? "on" : "off");
+	printf ("Bootsector is %swriteprotected\n",
+			((flashcom & 0x80) == 0x80) ? "not " : "");
+	switch ((can) & 0x3) {
+	case 0:
+		printf ("CAN Controller is on address 0x1000..0x10FF\n");
+		break;
+	case 1:
+		printf ("CAN Controller is on address 0x8000..0x80FF\n");
+		break;
+	case 2:
+		printf ("CAN Controller is on address 0xE000..0xE0FF\n");
+		break;
+	case 3:
+		printf ("CAN Controller is disabled\n");
+		break;
+	}
+	switch ((can >> 2) & 0x3) {
+	case 0:
+		printf ("CAN Controller Reset is ISA Reset\n");
+		break;
+	case 1:
+		printf ("CAN Controller Reset is ISA Reset and POS State\n");
+		break;
+	case 2:
+	case 3:
+		printf ("CAN Controller is in reset\n");
+		break;
+	}
+	if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
+		printf ("CAN Interrupt is disabled\n");
+	else
+		printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
+	switch (serpwr & 0x3) {
+	case 0:
+		printf ("SER0 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("SER0 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SER0 Drivers are disabled\n");
+		break;
+	}
+	switch ((serpwr >> 2) & 0x3) {
+	case 0:
+		printf ("SER1 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("SER1 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SER1 Drivers are disabled\n");
+		break;
+	}
+	switch (compwr & 0x3) {
+	case 0:
+		printf ("COM1 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("COM1 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("COM1 Drivers are disabled\n");
+		break;
+	}
+	switch ((compwr >> 2) & 0x3) {
+	case 0:
+		printf ("COM2 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("COM2 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("COM2 Drivers are disabled\n");
+		break;
+	}
+	switch ((nicvga) & 0x3) {
+	case 0:
+		printf ("PHY is running\n");
+		break;
+	case 1:
+		printf ("PHY is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("PHY is in Power save mode\n");
+		break;
+	}
+	switch ((nicvga >> 2) & 0x3) {
+	case 0:
+		printf ("VGA is running\n");
+		break;
+	case 1:
+		printf ("VGA is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("VGA is in Power save mode\n");
+		break;
+	}
+	printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
+	printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
+	printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
+			(nicvga >> 7) & 0x1);
+	switch ((scsirst) & 0x3) {
+	case 0:
+		printf ("SCSI Controller is running\n");
+		break;
+	case 1:
+		printf ("SCSI Controller is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SCSI Controller is in Power save mode\n");
+		break;
+	}
+	printf ("SCSI termination is %s\n",
+			((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
+	printf ("SCSI Controller is %sreseted\n",
+			((scsirst & 0x10) == 0x10) ? "" : "not ");
+	printf ("IDE disks are %sreseted\n",
+			((scsirst & 0x20) == 0x20) ? "" : "not ");
+	printf ("ISA Bus is %sreseted\n",
+			((scsirst & 0x40) == 0x40) ? "" : "not ");
+	printf ("Super IO is %sreseted\n",
+			((scsirst & 0x80) == 0x80) ? "" : "not ");
+}
+
+void user_led0 (unsigned char on)
+{
+	if (on == TRUE)
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
+	else
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
+}
+
+void user_led1 (unsigned char on)
+{
+	if (on == TRUE)
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
+	else
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
+}
+
+void ide_set_reset (int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	unsigned char resreg;
+
+	resreg = in8 (PLD_SCSI_RST_REG);
+	if (idereset == 1)
+		resreg |= 0x20;
+	else {
+		udelay(10000);
+		resreg &= 0xdf;
+	}
+	out8 (PLD_SCSI_RST_REG, resreg);
+}
+
+
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
new file mode 100644
index 0000000000..1dd7f3a4a1
--- /dev/null
+++ b/include/configs/MIP405.h
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************
+ * High Level Configuration Options
+ * (easy to change)
+ ***********************************************************/
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_MIP405		1	/* ...on a MIP405 board		*/
+/***********************************************************
+ * Clock
+ ***********************************************************/
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll   */
+
+/***********************************************************
+ * Command definitions
+ ***********************************************************/
+#define CONFIG_COMMANDS		\
+		       (CONFIG_CMD_DFL	| \
+			CFG_CMD_IDE	| \
+			CFG_CMD_DHCP	| \
+			CFG_CMD_CACHE	| \
+			CFG_CMD_PCI	| \
+			CFG_CMD_IRQ	| \
+			CFG_CMD_ECHO	| \
+			CFG_CMD_EEPROM	| \
+			CFG_CMD_I2C	| \
+			CFG_CMD_REGINFO | \
+			CFG_CMD_DATE	| \
+			CFG_CMD_ELF	| \
+			CFG_CMD_USB	| \
+			CFG_CMD_MII	| \
+			CFG_CMD_DOC	| \
+			CFG_CMD_SAVES	| \
+			CFG_CMD_BSP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
+#include <cmd_confdefs.h>
+
+#define	 CFG_HUSH_PARSER
+#define	 CFG_PROMPT_HUSH_PS2 "> "
+/**************************************************************
+ * I2C Stuff:
+ * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
+ * 0x53.
+ * The Atmel EEPROM uses 16Bit addressing.
+ ***************************************************************/
+
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x53	/* EEPROM 24C128/256		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
+					/* 64 byte page write mode using*/
+					/* last	6 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* enable Page write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x00000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x00800	/* 2k bytes may be used for env vars */
+
+/***************************************************************
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ ***************************************************************/
+#define SDRAM_EEPROM_WRITE_ADDRESS	0xA0
+#define SDRAM_EEPROM_READ_ADDRESS 	0xA1
+
+/**************************************************************
+ * Environment definitions
+ **************************************************************/
+#define CONFIG_BAUDRATE		9600	/* STD Baudrate */
+#define CONFIG_BOOTDELAY	5
+/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
+#define CONFIG_BOOT_RETRY_TIME	-10	/* feature is avaiable but not enabled */
+#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
+
+#define CONFIG_BOOTCOMMAND	"diskboot 200000 0:1; bootm" /* autoboot command		*/
+#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
+
+#define CONFIG_IPADDR		10.0.0.100
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_PREBOOT
+/***************************************************************
+ * defines if the console is stored in the environment
+ ***************************************************************/
+#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+/***************************************************************
+ * defines if an overwrite_console function exists
+ *************************************************************/
+#define CFG_CONSOLE_OVERWRITE_ROUTINE
+#define CFG_CONSOLE_INFO_QUIET
+/***************************************************************
+ * defines if the overwrite_console should be stored in the
+ * environment
+ **************************************************************/
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+/**************************************************************
+ * loads config
+ *************************************************************/
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MISC_INIT_R
+/***********************************************************
+ * Miscellaneous configurable options
+ **********************************************************/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_BASE_BAUD       916667
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x200000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
+#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
+					/* resource configuration	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+#define CONFIG_BOARD_PRE_INIT
+
+/* Peripheral Bus Mapping */
+#define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_UART0_ADDR		0xF4100000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_UART1_ADDR		0xF4200000 /* smallest window is 1MByte 0x10 0000*/
+
+#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
+#define CONFIG_PORT_ADDR 	PER_PLD_ADDR + 5
+
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in On Chip SRAM)
+ */
+#define CFG_TEMP_STACK_OCM      1
+#define CFG_OCM_DATA_ADDR	0xF0000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+/***********************************************************************
+ * External peripheral base address
+ ***********************************************************************/
+#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+/************************************************************
+ * Ethernet Stuff
+ ***********************************************************/
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/************************************************************
+ * IDE/ATA stuff
+ ************************************************************/
+#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */
+#define CFG_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
+#define CFG_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
+#define CFG_ATA_DATA_OFFSET	0		/* data reg offset	*/
+#define CFG_ATA_REG_OFFSET 	0		/* reg offset */
+#define CFG_ATA_ALT_OFFSET	0x200		/* alternate register offset */
+
+#undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED	       /* no led for ide supported     */
+#define CONFIG_IDE_RESET       /* reset for ide supported...	*/
+#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
+
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI			/* enable ATAPI Support */
+
+/************************************************************
+ * SCSI support (experimental) only SYM53C8xx supported
+ ************************************************************/
+#undef CONFIG_SCSI_SYM53C8XX
+
+#ifdef CONFIG_SCSI_SYM53C8XX
+#define CFG_SCSI_MAX_LUN	8 /* number of supported LUNs */
+#define CFG_SCSI_MAX_SCSI_ID	7 /* maximum SCSI ID (0..6) */
+#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
+#define CFG_SCSI_SPIN_UP_TIME	2
+#endif /* CONFIG_SCSI_SYM53C8XX */
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+/************************************************************
+ * Keyboard support
+ ************************************************************/
+#undef CONFIG_ISA_KEYBOARD
+
+/************************************************************
+ * Video support
+ ************************************************************/
+#define CONFIG_VIDEO			/*To enable video controller support */
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#undef CONFIG_VIDEO_ONBOARD
+/************************************************************
+ * USB support EXPERIMENTAL
+ ************************************************************/
+#define CONFIG_USB_UHCI
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_USB_STORAGE
+
+/* Enable needed helper functions */
+#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
+
+/************************************************************
+ * Debug support
+ ************************************************************/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/************************************************************
+ * Ident
+ ************************************************************/
+#define VERSION_TAG "released"
+#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, MEV-10072-001 " VERSION_TAG
+
+
+#endif	/* __CONFIG_H */