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| author | Simon Glass <sjg@chromium.org> | 2015-10-18 19:51:27 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-10-21 07:46:50 -0600 |
| commit | 7b95252d82267143e647d5fee96c7d9d5bf74560 (patch) | |
| tree | ec92539c590c51b03aa04ef7ff0a7ef439226e1f | |
| parent | 60994a02a56fd7dc408b0a36ad5dead1b85959b4 (diff) | |
| download | talos-obmc-uboot-7b95252d82267143e647d5fee96c7d9d5bf74560.tar.gz talos-obmc-uboot-7b95252d82267143e647d5fee96c7d9d5bf74560.zip | |
x86: chromebook_link: Enable the debug UART
Add support for the debug UART on link. This is useful for early debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 7 | ||||
| -rw-r--r-- | configs/chromebook_link_defconfig | 4 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index cce5923f0b..0e6512c675 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -340,3 +340,10 @@ int print_cpuinfo(void) return 0; } + +void board_debug_uart_init(void) +{ + /* This enables the debug UART */ + pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, + PCI_SIZE_16); +} diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index fbecf8bea9..78a9470622 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -22,6 +22,10 @@ CONFIG_CROS_EC_LPC=y CONFIG_SPI_FLASH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DM_TPM=y CONFIG_TPM_TIS_LPC=y CONFIG_VIDEO_VESA=y |
