diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | talos-obmc-uboot-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz talos-obmc-uboot-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2039 files changed, 53844 insertions, 53844 deletions
@@ -1701,7 +1701,7 @@ ISPAN_config \ ISPAN_REVB_config: unconfig @mkdir -p $(obj)include @if [ "$(findstring _REVB_,$@)" ] ; then \ - echo "#define CFG_REV_B" > $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_REV_B" > $(obj)include/config.h ; \ fi @$(MKCONFIG) -a ISPAN ppc mpc8260 ispan @@ -1728,8 +1728,8 @@ PQ2FADS-ZU_66MHz_lowboot_config \ @mkdir -p $(obj)include @mkdir -p $(obj)board/freescale/mpc8260ads $(if $(findstring PQ2FADS,$@), \ - @echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \ - @echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h) + @echo "#define CONFIG_ADSTYPE CONFIG_SYS_PQ2FADS" > $(obj)include/config.h, \ + @echo "#define CONFIG_ADSTYPE CONFIG_SYS_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h) $(if $(findstring MHz,$@), \ @echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \ $(if $(findstring VR,$@), \ @@ -1981,19 +1981,19 @@ M54451EVB_stmicro_config : unconfig M54451EVB_stmicro_config) FLASH=STMICRO;; \ esac; \ if [ "$${FLASH}" = "SPANSION" ] ; then \ - echo "#define CFG_SPANSION_BOOT" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \ cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \ $(XECHO) "... with SPANSION boot..." ; \ fi; \ if [ "$${FLASH}" = "STMICRO" ] ; then \ echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \ - echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \ cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \ $(XECHO) "... with ST Micro boot..." ; \ fi; \ - echo "#define CFG_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ; + echo "#define CONFIG_SYS_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ; @$(MKCONFIG) -a M54451EVB m68k mcf5445x m54451evb freescale M54455EVB_config \ @@ -2015,25 +2015,25 @@ M54455EVB_stm33_config : unconfig M54455EVB_stm33_config) FLASH=STMICRO; FREQ=33333333;; \ esac; \ if [ "$${FLASH}" = "INTEL" ] ; then \ - echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_INTEL_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \ $(XECHO) "... with INTEL boot..." ; \ fi; \ if [ "$${FLASH}" = "ATMEL" ] ; then \ - echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_ATMEL_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \ $(XECHO) "... with ATMEL boot..." ; \ fi; \ if [ "$${FLASH}" = "STMICRO" ] ; then \ echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \ - echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \ cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \ $(XECHO) "... with ST Micro boot..." ; \ fi; \ - echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ $(XECHO) "... with $${FREQ}Hz input clock" @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale @@ -2053,20 +2053,20 @@ M5475GFE_config : unconfig M5475FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \ M5475GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \ esac; \ - echo "#define CFG_BUSCLK 133333333" > $(obj)include/config.h ; \ - echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \ - echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_BUSCLK 133333333" > $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \ if [ "$${RAM1}" != "0" ] ; then \ - echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \ fi; \ if [ "$${CODE}" != "0" ] ; then \ - echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \ fi; \ if [ "$${VID}" == "1" ] ; then \ - echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \ fi; \ if [ "$${USB}" == "1" ] ; then \ - echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \ fi @$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale @@ -2088,20 +2088,20 @@ M5485HFE_config : unconfig M5485GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \ M5485HFE_config) BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \ esac; \ - echo "#define CFG_BUSCLK 100000000" > $(obj)include/config.h ; \ - echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \ - echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_BUSCLK 100000000" > $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \ if [ "$${RAM1}" != "0" ] ; then \ - echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \ fi; \ if [ "$${CODE}" != "0" ] ; then \ - echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \ fi; \ if [ "$${VID}" == "1" ] ; then \ - echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \ fi; \ if [ "$${USB}" == "1" ] ; then \ - echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \ + echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \ fi @$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale @@ -2120,11 +2120,11 @@ MPC8313ERDB_NAND_66_config: unconfig @mkdir -p $(obj)board/freescale/mpc8313erdb @if [ "$(findstring _33_,$@)" ] ; then \ $(XECHO) -n "...33M ..." ; \ - echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \ + echo "#define CONFIG_SYS_33MHZ" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ $(XECHO) -n "...66M..." ; \ - echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \ + echo "#define CONFIG_SYS_66MHZ" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _NAND_,$@)" ] ; then \ $(XECHO) -n "...NAND..." ; \ @@ -210,7 +210,7 @@ There are two classes of configuration variables: * Configuration _SETTINGS_: These depend on the hardware etc. and should not be meddled with if you don't know what you're doing; they have names beginning with - "CFG_". + "CONFIG_SYS_". Later we will add a configuration tool - probably similar to or even identical to what's used for the Linux kernel. Right now, we have to @@ -284,10 +284,10 @@ The following options need to be configured: - Board flavour: (if CONFIG_MPC8260ADS is defined) CONFIG_ADSTYPE Possible values are: - CFG_8260ADS - original MPC8260ADS - CFG_8266ADS - MPC8266ADS - CFG_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR - CFG_8272ADS - MPC8272ADS + CONFIG_SYS_8260ADS - original MPC8260ADS + CONFIG_SYS_8266ADS - MPC8266ADS + CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR + CONFIG_SYS_8272ADS - MPC8272ADS - MPC824X Family Member (if CONFIG_MPC824X is defined) Define exactly one of @@ -302,28 +302,28 @@ The following options need to be configured: or XTAL/EXTAL) - 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU): - CFG_8xx_CPUCLK_MIN - CFG_8xx_CPUCLK_MAX + CONFIG_SYS_8xx_CPUCLK_MIN + CONFIG_SYS_8xx_CPUCLK_MAX CONFIG_8xx_CPUCLK_DEFAULT See doc/README.MPC866 - CFG_MEASURE_CPUCLK + CONFIG_SYS_MEASURE_CPUCLK Define this to measure the actual CPU clock instead of relying on the correctness of the configured values. Mostly useful for board bringup to make sure the PLL is locked at the intended frequency. Note that this requires a (stable) reference clock (32 kHz - RTC clock or CFG_8XX_XIN) + RTC clock or CONFIG_SYS_8XX_XIN) - Intel Monahans options: - CFG_MONAHANS_RUN_MODE_OSC_RATIO + CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO Defines the Monahans run mode to oscillator ratio. Valid values are 8, 16, 24, 31. The core frequency is this value multiplied by 13 MHz. - CFG_MONAHANS_TURBO_RUN_MODE_RATIO + CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO Defines the Monahans turbo mode to oscillator ratio. Valid values are 1 (default if undefined) and @@ -436,7 +436,7 @@ The following options need to be configured: CONFIG_CONSOLE_CURSOR cursor drawing on/off (requires blink timer cf. i8042.c) - CFG_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c) + CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c) CONFIG_CONSOLE_TIME display time/date info in upper right corner (requires CONFIG_CMD_DATE) @@ -461,8 +461,8 @@ The following options need to be configured: - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in - CFG_BAUDRATE_TABLE, see below. - CFG_BRGCLK_PRESCALE, baudrate prescale + CONFIG_SYS_BAUDRATE_TABLE, see below. + CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale - Interrupt driven serial port input: CONFIG_SERIAL_SOFTWARE_FIFO @@ -546,7 +546,7 @@ The following options need to be configured: - Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined) CONFIG_KGDB_BAUDRATE Select one of the baudrates listed in - CFG_BAUDRATE_TABLE, see below. + CONFIG_SYS_BAUDRATE_TABLE, see below. - Monitor Functions: Monitor commands can be included or excluded @@ -673,7 +673,7 @@ The following options need to be configured: CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC - CFG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 + CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 Note that if the RTC uses I2C, then the I2C interface must also be configured. See I2C Support, below. @@ -711,11 +711,11 @@ The following options need to be configured: CONFIG_LBA48 Set this to enable support for disks larger than 137GB - Also look at CFG_64BIT_LBA ,CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL + Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL Whithout these , LBA48 support uses 32bit variables and will 'only' support disks up to 2.1TB. - CFG_64BIT_LBA: + CONFIG_SYS_64BIT_LBA: When enabled, makes the IDE subsystem use 64bit sector addresses. Default is 32bit. @@ -724,12 +724,12 @@ The following options need to be configured: SYM53C8XX SCSI controller; define CONFIG_SCSI_SYM53C8XX to enable it. - CFG_SCSI_MAX_LUN [8], CFG_SCSI_MAX_SCSI_ID [7] and - CFG_SCSI_MAX_DEVICE [CFG_SCSI_MAX_SCSI_ID * - CFG_SCSI_MAX_LUN] can be adjusted to define the + CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and + CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID * + CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the maximum numbers of LUNs, SCSI ID's and target devices. - CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) + CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) - NETWORK Support (PCI): CONFIG_E1000 @@ -811,7 +811,7 @@ The following options need to be configured: CONFIG_USB_CONFIG for differential drivers: 0x00001000 for single ended drivers: 0x00005000 - CFG_USB_EVENT_POLL + CONFIG_SYS_USB_EVENT_POLL May be defined to allow interrupt polling instead of using asynchronous interrupts @@ -838,18 +838,18 @@ The following options need to be configured: Define this to have a tty type of device available to talk to the UDC device - CFG_CONSOLE_IS_IN_ENV + CONFIG_SYS_CONSOLE_IS_IN_ENV Define this if you want stdin, stdout &/or stderr to be set to usbtty. mpc8xx: - CFG_USB_EXTC_CLK 0xBLAH + CONFIG_SYS_USB_EXTC_CLK 0xBLAH Derive USB clock from external clock "blah" - - CFG_USB_EXTC_CLK 0x02 + - CONFIG_SYS_USB_EXTC_CLK 0x02 - CFG_USB_BRG_CLK 0xBLAH + CONFIG_SYS_USB_BRG_CLK 0xBLAH Derive USB clock from brgclk - - CFG_USB_BRG_CLK 0x04 + - CONFIG_SYS_USB_BRG_CLK 0x04 If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h @@ -891,16 +891,16 @@ The following options need to be configured: CONFIG_JFFS2_NAND_DEV Define these for a default partition on a NAND device - CFG_JFFS2_FIRST_SECTOR, - CFG_JFFS2_FIRST_BANK, CFG_JFFS2_NUM_BANKS + CONFIG_SYS_JFFS2_FIRST_SECTOR, + CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS Define these for a default partition on a NOR device - CFG_JFFS_CUSTOM_PART + CONFIG_SYS_JFFS_CUSTOM_PART Define this to create an own partition. You have to provide a function struct part_info* jffs2_part_info(int part_num) If you define only one JFFS2 partition you may also want to - #define CFG_JFFS_SINGLE_PART 1 + #define CONFIG_SYS_JFFS_SINGLE_PART 1 to disable the command chpart. This is the default when you have not defined a custom partition @@ -1014,7 +1014,7 @@ The following options need to be configured: 320x240. Black & white. Normally display is black on white background; define - CFG_WHITE_ON_BLACK to get it inverted. + CONFIG_SYS_WHITE_ON_BLACK to get it inverted. - Splash Screen Support: CONFIG_SPLASH_SCREEN @@ -1041,7 +1041,7 @@ The following options need to be configured: compressed images are supported. NOTE: the bzip2 algorithm requires a lot of RAM, so - the malloc area (as defined by CFG_MALLOC_LEN) should + the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should be at least 4MB. CONFIG_LZMA @@ -1065,7 +1065,7 @@ The following options need to be configured: Use the lzmainfo tool to determinate the lc and lp values and then calculate the amount of needed dynamic memory (ensuring - the appropriate CFG_MALLOC_LEN value). + the appropriate CONFIG_SYS_MALLOC_LEN value). - MII/PHY support: CONFIG_PHY_ADDR @@ -1282,15 +1282,15 @@ The following options need to be configured: There are several other quantities that must also be defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C. - In both cases you will need to define CFG_I2C_SPEED + In both cases you will need to define CONFIG_SYS_I2C_SPEED to be the frequency (in Hz) at which you wish your i2c bus - to run and CFG_I2C_SLAVE to be the address of this node (ie + to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie the CPU's i2c node address). Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c) sets the CPU up as a master node and so its address should therefore be cleared to 0 (See, eg, MPC823e User's Manual - p.16-473). So, set CFG_I2C_SLAVE to 0. + p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0. That's all that's required for CONFIG_HARD_I2C. @@ -1361,7 +1361,7 @@ The following options need to be configured: #define I2C_DELAY udelay(2) - CFG_I2C_INIT_BOARD + CONFIG_SYS_I2C_INIT_BOARD When a board is reset during an i2c bus transfer chips might think that the current transfer is still @@ -1385,7 +1385,7 @@ The following options need to be configured: active. To switch to a different bus, use the 'i2c dev' command. Note that bus numbering is zero-based. - CFG_I2C_NOPROBES + CONFIG_SYS_I2C_NOPROBES This option specifies a list of I2C devices that will be skipped when the 'i2c probe' command is issued (or 'iprobe' using the legacy @@ -1394,31 +1394,31 @@ The following options need to be configured: e.g. #undef CONFIG_I2C_MULTI_BUS - #define CFG_I2C_NOPROBES {0x50,0x68} + #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68} will skip addresses 0x50 and 0x68 on a board with one I2C bus #define CONFIG_I2C_MULTI_BUS - #define CFG_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} + #define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CFG_SPD_BUS_NUM + CONFIG_SYS_SPD_BUS_NUM If defined, then this indicates the I2C bus number for DDR SPD. If not defined, then U-Boot assumes that SPD is on I2C bus 0. - CFG_RTC_BUS_NUM + CONFIG_SYS_RTC_BUS_NUM If defined, then this indicates the I2C bus number for the RTC. If not defined, then U-Boot assumes that RTC is on I2C bus 0. - CFG_DTT_BUS_NUM + CONFIG_SYS_DTT_BUS_NUM If defined, then this indicates the I2C bus number for the DTT. If not defined, then U-Boot assumes that DTT is on I2C bus 0. - CFG_I2C_DTT_ADDR: + CONFIG_SYS_I2C_DTT_ADDR: If defined, specifies the I2C address of the DTT device. If not defined, then U-Boot uses predefined value for @@ -1529,11 +1529,11 @@ The following options need to be configured: Specify the number of FPGA devices to support. - CFG_FPGA_PROG_FEEDBACK + CONFIG_SYS_FPGA_PROG_FEEDBACK Enable printing of hash marks during FPGA configuration. - CFG_FPGA_CHECK_BUSY + CONFIG_SYS_FPGA_CHECK_BUSY Enable checks on FPGA configuration interface busy status by the configuration function. This option @@ -1545,29 +1545,29 @@ The following options need to be configured: If defined, a function that provides delays in the FPGA configuration driver. - CFG_FPGA_CHECK_CTRLC + CONFIG_SYS_FPGA_CHECK_CTRLC Allow Control-C to interrupt FPGA configuration - CFG_FPGA_CHECK_ERROR + CONFIG_SYS_FPGA_CHECK_ERROR Check for configuration errors during FPGA bitfile loading. For example, abort during Virtex II configuration if the INIT_B line goes low (which indicated a CRC error). - CFG_FPGA_WAIT_INIT + CONFIG_SYS_FPGA_WAIT_INIT Maximum time to wait for the INIT_B line to deassert after PROB_B has been deasserted during a Virtex II FPGA configuration sequence. The default time is 500 ms. - CFG_FPGA_WAIT_BUSY + CONFIG_SYS_FPGA_WAIT_BUSY Maximum time to wait for BUSY to deassert during Virtex II FPGA configuration. The default is 5 ms. - CFG_FPGA_WAIT_CONFIG + CONFIG_SYS_FPGA_WAIT_CONFIG Time to wait after FPGA configuration. The default is 200 ms. @@ -1665,7 +1665,7 @@ The following options need to be configured: for the "hush" shell. - CFG_HUSH_PARSER + CONFIG_SYS_HUSH_PARSER Define this variable to enable the "hush" shell (from Busybox) as command line interpreter, thus enabling @@ -1677,7 +1677,7 @@ The following options need to be configured: with a somewhat smaller memory footprint. - CFG_PROMPT_HUSH_PS2 + CONFIG_SYS_PROMPT_HUSH_PS2 This defines the secondary prompt string, which is printed when the command interpreter needs more input @@ -1749,10 +1749,10 @@ The following options need to be configured: Adding this option adds support for Xilinx SystemACE chips attached via some sort of local bus. The address of the chip must also be defined in the - CFG_SYSTEMACE_BASE macro. For example: + CONFIG_SYS_SYSTEMACE_BASE macro. For example: #define CONFIG_SYSTEMACE - #define CFG_SYSTEMACE_BASE 0xf0000000 + #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000 When SystemACE support is added, the "ace" device type becomes available to the fat commands, i.e. fatls. @@ -2000,53 +2000,53 @@ Modem Support: Configuration Settings: ----------------------- -- CFG_LONGHELP: Defined when you want long help messages included; +- CONFIG_SYS_LONGHELP: Defined when you want long help messages included; undefine this when you're short of memory. -- CFG_PROMPT: This is what U-Boot prints on the console to +- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to prompt for user input. -- CFG_CBSIZE: Buffer size for input from the Console +- CONFIG_SYS_CBSIZE: Buffer size for input from the Console -- CFG_PBSIZE: Buffer size for Console output +- CONFIG_SYS_PBSIZE: Buffer size for Console output -- CFG_MAXARGS: max. Number of arguments accepted for monitor commands +- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands -- CFG_BARGSIZE: Buffer size for Boot Arguments which are passed to +- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to the application (usually a Linux kernel) when it is booted -- CFG_BAUDRATE_TABLE: +- CONFIG_SYS_BAUDRATE_TABLE: List of legal baudrate settings for this board. -- CFG_CONSOLE_INFO_QUIET +- CONFIG_SYS_CONSOLE_INFO_QUIET Suppress display of console information at boot. -- CFG_CONSOLE_IS_IN_ENV +- CONFIG_SYS_CONSOLE_IS_IN_ENV If the board specific function extern int overwrite_console (void); returns 1, the stdin, stderr and stdout are switched to the serial port, else the settings in the environment are used. -- CFG_CONSOLE_OVERWRITE_ROUTINE +- CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE Enable the call to overwrite_console(). -- CFG_CONSOLE_ENV_OVERWRITE +- CONFIG_SYS_CONSOLE_ENV_OVERWRITE Enable overwrite of previous console environment settings. -- CFG_MEMTEST_START, CFG_MEMTEST_END: +- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END: Begin and End addresses of the area used by the simple memory test. -- CFG_ALT_MEMTEST: +- CONFIG_SYS_ALT_MEMTEST: Enable an alternate, more extensive memory test. -- CFG_MEMTEST_SCRATCH: +- CONFIG_SYS_MEMTEST_SCRATCH: Scratch address used by the alternate memory test You only need to set this if address zero isn't writeable -- CFG_MEM_TOP_HIDE (PPC only): - If CFG_MEM_TOP_HIDE is defined in the board config header, +- CONFIG_SYS_MEM_TOP_HIDE (PPC only): + If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of RAM and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed @@ -2066,75 +2066,75 @@ Configuration Settings: non page size aligned address and this could cause major problems. -- CFG_TFTP_LOADADDR: +- CONFIG_SYS_TFTP_LOADADDR: Default load address for network file downloads -- CFG_LOADS_BAUD_CHANGE: +- CONFIG_SYS_LOADS_BAUD_CHANGE: Enable temporary baudrate change while serial download -- CFG_SDRAM_BASE: +- CONFIG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here. -- CFG_MBIO_BASE: +- CONFIG_SYS_MBIO_BASE: Physical start address of Motherboard I/O (if using a Cogent motherboard) -- CFG_FLASH_BASE: +- CONFIG_SYS_FLASH_BASE: Physical start address of Flash memory. -- CFG_MONITOR_BASE: +- CONFIG_SYS_MONITOR_BASE: Physical start address of boot monitor code (set by make config files to be same as the text base address (TEXT_BASE) used when linking) - same as - CFG_FLASH_BASE when booting from flash. + CONFIG_SYS_FLASH_BASE when booting from flash. -- CFG_MONITOR_LEN: +- CONFIG_SYS_MONITOR_LEN: Size of memory reserved for monitor code, used to determine _at_compile_time_ (!) if the environment is embedded within the U-Boot image, or in a separate flash sector. -- CFG_MALLOC_LEN: +- CONFIG_SYS_MALLOC_LEN: Size of DRAM reserved for malloc() use. -- CFG_BOOTM_LEN: +- CONFIG_SYS_BOOTM_LEN: Normally compressed uImages are limited to an uncompressed size of 8 MBytes. If this is not enough, - you can define CFG_BOOTM_LEN in your board config file + you can define CONFIG_SYS_BOOTM_LEN in your board config file to adjust this setting to your needs. -- CFG_BOOTMAPSZ: +- CONFIG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by the Linux kernel (bd_info, boot arguments, FDT blob if used) must be put below this limit, unless "bootm_low" enviroment variable is defined and non-zero. In such case all data for the Linux kernel must be between "bootm_low" - and "bootm_low" + CFG_BOOTMAPSZ. + and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. -- CFG_MAX_FLASH_BANKS: +- CONFIG_SYS_MAX_FLASH_BANKS: Max number of Flash memory banks -- CFG_MAX_FLASH_SECT: +- CONFIG_SYS_MAX_FLASH_SECT: Max number of sectors on a Flash chip -- CFG_FLASH_ERASE_TOUT: +- CONFIG_SYS_FLASH_ERASE_TOUT: Timeout for Flash erase operations (in ms) -- CFG_FLASH_WRITE_TOUT: +- CONFIG_SYS_FLASH_WRITE_TOUT: Timeout for Flash write operations (in ms) -- CFG_FLASH_LOCK_TOUT +- CONFIG_SYS_FLASH_LOCK_TOUT Timeout for Flash set sector lock bit operation (in ms) -- CFG_FLASH_UNLOCK_TOUT +- CONFIG_SYS_FLASH_UNLOCK_TOUT Timeout for Flash clear lock bits operation (in ms) -- CFG_FLASH_PROTECTION +- CONFIG_SYS_FLASH_PROTECTION If defined, hardware flash sectors protection is used instead of U-Boot software protection. -- CFG_DIRECT_FLASH_TFTP: +- CONFIG_SYS_DIRECT_FLASH_TFTP: Enable TFTP transfers directly to flash memory; without this option such a download has to be @@ -2147,7 +2147,7 @@ Configuration Settings: too limited to allow for a temporary copy of the downloaded image) this option may be very useful. -- CFG_FLASH_CFI: +- CONFIG_SYS_FLASH_CFI: Define if the flash driver uses extra elements in the common flash structure for storing flash geometry. @@ -2155,14 +2155,14 @@ Configuration Settings: This option also enables the building of the cfi_flash driver in the drivers directory -- CFG_FLASH_USE_BUFFER_WRITE +- CONFIG_SYS_FLASH_USE_BUFFER_WRITE Use buffered writes to flash. - CONFIG_FLASH_SPANSION_S29WS_N s29ws-n MirrorBit flash has non-standard addresses for buffered write commands. -- CFG_FLASH_QUIET_TEST +- CONFIG_SYS_FLASH_QUIET_TEST If this option is defined, the common CFI flash doesn't print it's warning upon not recognized FLASH banks. This is useful, if some of the configured banks are only @@ -2173,7 +2173,7 @@ Configuration Settings: digits and dots. Recommended value: 45 (9..1) for 80 column displays, 15 (3..1) for 40 column displays. -- CFG_RX_ETH_BUFFER: +- CONFIG_SYS_RX_ETH_BUFFER: Defines the number of Ethernet receive buffers. On some Ethernet controllers it is recommended to set this value to 8 or even higher (EEPRO100 or 405 EMAC), since all @@ -2208,7 +2208,7 @@ following configurations: type flash chips the second sector can be used: the offset for this sector is given here. - CONFIG_ENV_OFFSET is used relative to CFG_FLASH_BASE. + CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE. - CONFIG_ENV_ADDR: @@ -2291,24 +2291,24 @@ to save the current settings. These two #defines specify the offset and size of the environment area within the total memory of your EEPROM. - - CFG_I2C_EEPROM_ADDR: + - CONFIG_SYS_I2C_EEPROM_ADDR: If defined, specified the chip address of the EEPROM device. The default address is zero. - - CFG_EEPROM_PAGE_WRITE_BITS: + - CONFIG_SYS_EEPROM_PAGE_WRITE_BITS: If defined, the number of bits used to address bytes in a single page in the EEPROM device. A 64 byte page, for example would require six bits. - - CFG_EEPROM_PAGE_WRITE_DELAY_MS: + - CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS: If defined, the number of milliseconds to delay between page writes. The default is zero milliseconds. - - CFG_I2C_EEPROM_ADDR_LEN: + - CONFIG_SYS_I2C_EEPROM_ADDR_LEN: The length in bytes of the EEPROM memory array address. Note that this is NOT the chip address length! - - CFG_I2C_EEPROM_ADDR_OVERFLOW: + - CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW: EEPROM chips that implement "address overflow" are ones like Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the extra bits end up in the "chip address" bit @@ -2319,7 +2319,7 @@ to save the current settings. still be one byte because the extra address bits are hidden in the chip address. - - CFG_EEPROM_SIZE: + - CONFIG_SYS_EEPROM_SIZE: The size in bytes of the EEPROM device. @@ -2358,7 +2358,7 @@ to save the current settings. to a block boundary, and CONFIG_ENV_SIZE must be a multiple of the NAND devices block size. -- CFG_SPI_INIT_OFFSET +- CONFIG_SYS_SPI_INIT_OFFSET Defines offset to the initial SPI buffer area in DPRAM. The area is used at an early stage (ROM part) if the environment @@ -2384,29 +2384,29 @@ Note: once the monitor has been relocated, then it will complain if the default environment is used; a new CRC is computed as soon as you use the "saveenv" command to store a valid environment. -- CFG_FAULT_ECHO_LINK_DOWN: +- CONFIG_SYS_FAULT_ECHO_LINK_DOWN: Echo the inverted Ethernet link state to the fault LED. - Note: If this option is active, then CFG_FAULT_MII_ADDR + Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR also needs to be defined. -- CFG_FAULT_MII_ADDR: +- CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state. -- CFG_64BIT_VSPRINTF: +- CONFIG_SYS_64BIT_VSPRINTF: Makes vsprintf (and all *printf functions) support printing of 64bit values by using the L quantifier -- CFG_64BIT_STRTOUL: +- CONFIG_SYS_64BIT_STRTOUL: Adds simple_strtoull that returns a 64bit value Low Level (hardware related) configuration options: --------------------------------------------------- -- CFG_CACHELINE_SIZE: +- CONFIG_SYS_CACHELINE_SIZE: Cache Line Size of the CPU. -- CFG_DEFAULT_IMMR: +- CONFIG_SYS_DEFAULT_IMMR: Default address of the IMMR after system reset. Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, @@ -2414,36 +2414,36 @@ Low Level (hardware related) configuration options: the IMMR register after a reset. - Floppy Disk Support: - CFG_FDC_DRIVE_NUMBER + CONFIG_SYS_FDC_DRIVE_NUMBER the default drive number (default value 0) - CFG_ISA_IO_STRIDE + CONFIG_SYS_ISA_IO_STRIDE defines the spacing between FDC chipset registers (default value 1) - CFG_ISA_IO_OFFSET + CONFIG_SYS_ISA_IO_OFFSET defines the offset of register from address. It depends on which part of the data bus is connected to the FDC chipset. (default value 0) - If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and - CFG_FDC_DRIVE_NUMBER are undefined, they take their + If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and + CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their default value. - if CFG_FDC_HW_INIT is defined, then the function + if CONFIG_SYS_FDC_HW_INIT is defined, then the function fdc_hw_init() is called at the beginning of the FDC setup. fdc_hw_init() must be provided by the board source code. It is used to make hardware dependant initializations. -- CFG_IMMR: Physical address of the Internal Memory. +- CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're doing! (11-4) [MPC8xx/82xx systems only] -- CFG_INIT_RAM_ADDR: +- CONFIG_SYS_INIT_RAM_ADDR: Start address of memory area that can be used for initial data and stack; please note that this must be @@ -2458,91 +2458,91 @@ Low Level (hardware related) configuration options: - MPC824X: data cache - PPC4xx: data cache -- CFG_GBL_DATA_OFFSET: +- CONFIG_SYS_GBL_DATA_OFFSET: Offset of the initial data structure in the memory - area defined by CFG_INIT_RAM_ADDR. Usually - CFG_GBL_DATA_OFFSET is chosen such that the initial + area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually + CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial data is located at the end of the available space - (sometimes written as (CFG_INIT_RAM_END - - CFG_INIT_DATA_SIZE), and the initial stack is just - below that area (growing from (CFG_INIT_RAM_ADDR + - CFG_GBL_DATA_OFFSET) downward. + (sometimes written as (CONFIG_SYS_INIT_RAM_END - + CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just + below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR + + CONFIG_SYS_GBL_DATA_OFFSET) downward. Note: On the MPC824X (or other systems that use the data cache for initial memory) the address chosen for - CFG_INIT_RAM_ADDR is basically arbitrary - it must + CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must point to an otherwise UNUSED address space between the top of RAM and the start of the PCI space. -- CFG_SIUMCR: SIU Module Configuration (11-6) +- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6) -- CFG_SYPCR: System Protection Control (11-9) +- CONFIG_SYS_SYPCR: System Protection Control (11-9) -- CFG_TBSCR: Time Base Status and Control (11-26) +- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26) -- CFG_PISCR: Periodic Interrupt Status and Control (11-31) +- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31) -- CFG_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) +- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) -- CFG_SCCR: System Clock and reset Control Register (15-27) +- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27) -- CFG_OR_TIMING_SDRAM: +- CONFIG_SYS_OR_TIMING_SDRAM: SDRAM timing -- CFG_MAMR_PTA: +- CONFIG_SYS_MAMR_PTA: periodic timer for refresh -- CFG_DER: Debug Event Register (37-47) +- CONFIG_SYS_DER: Debug Event Register (37-47) -- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CFG_REMAP_OR_AM, - CFG_PRELIM_OR_AM, CFG_OR_TIMING_FLASH, CFG_OR0_REMAP, - CFG_OR0_PRELIM, CFG_BR0_PRELIM, CFG_OR1_REMAP, CFG_OR1_PRELIM, - CFG_BR1_PRELIM: +- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM, + CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP, + CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM, + CONFIG_SYS_BR1_PRELIM: Memory Controller Definitions: BR0/1 and OR0/1 (FLASH) - SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE, - CFG_OR_TIMING_SDRAM, CFG_OR2_PRELIM, CFG_BR2_PRELIM, - CFG_OR3_PRELIM, CFG_BR3_PRELIM: + CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM, + CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM: Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM) -- CFG_MAMR_PTA, CFG_MPTPR_2BK_4K, CFG_MPTPR_1BK_4K, CFG_MPTPR_2BK_8K, - CFG_MPTPR_1BK_8K, CFG_MAMR_8COL, CFG_MAMR_9COL: +- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K, + CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL: Machine Mode Register and Memory Periodic Timer Prescaler definitions (SDRAM timing) -- CFG_I2C_UCODE_PATCH, CFG_I2C_DPMEM_OFFSET [0x1FC0]: +- CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]: enable I2C microcode relocation patch (MPC8xx); define relocation offset in DPRAM [DSP2] -- CFG_SMC_UCODE_PATCH, CFG_SMC_DPMEM_OFFSET [0x1FC0]: +- CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]: enable SMC microcode relocation patch (MPC8xx); define relocation offset in DPRAM [SMC1] -- CFG_SPI_UCODE_PATCH, CFG_SPI_DPMEM_OFFSET [0x1FC0]: +- CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]: enable SPI microcode relocation patch (MPC8xx); define relocation offset in DPRAM [SCC4] -- CFG_USE_OSCCLK: +- CONFIG_SYS_USE_OSCCLK: Use OSCM clock mode on MBX8xx board. Be careful, wrong setting might damage your board. Read doc/README.MBX before setting this variable! -- CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) +- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) Offset of the bootmode word in DPRAM used by post (Power On Self Tests). This definition overrides #define'd default value in commproc.h resp. cpm_8260.h. -- CFG_PCI_SLV_MEM_LOCAL, CFG_PCI_SLV_MEM_BUS, CFG_PICMR0_MASK_ATTRIB, - CFG_PCI_MSTR0_LOCAL, CFG_PCIMSK0_MASK, CFG_PCI_MSTR1_LOCAL, - CFG_PCIMSK1_MASK, CFG_PCI_MSTR_MEM_LOCAL, CFG_PCI_MSTR_MEM_BUS, - CFG_CPU_PCI_MEM_START, CFG_PCI_MSTR_MEM_SIZE, CFG_POCMR0_MASK_ATTRIB, - CFG_PCI_MSTR_MEMIO_LOCAL, CFG_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, - CFG_PCI_MSTR_MEMIO_SIZE, CFG_POCMR1_MASK_ATTRIB, CFG_PCI_MSTR_IO_LOCAL, - CFG_PCI_MSTR_IO_BUS, CFG_CPU_PCI_IO_START, CFG_PCI_MSTR_IO_SIZE, - CFG_POCMR2_MASK_ATTRIB: (MPC826x only) +- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB, + CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL, + CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS, + CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB, + CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL, + CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE, + CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only) Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. - CONFIG_SPD_EEPROM @@ -2552,16 +2552,16 @@ Low Level (hardware related) configuration options: SPD_EEPROM_ADDRESS I2C address of the SPD EEPROM -- CFG_SPD_BUS_NUM +- CONFIG_SYS_SPD_BUS_NUM If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve to something your driver can deal with. -- CFG_83XX_DDR_USES_CS0 +- CONFIG_SYS_83XX_DDR_USES_CS0 Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. -- CFG_83XX_DDR_USES_CS0 +- CONFIG_SYS_83XX_DDR_USES_CS0 Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. @@ -2861,7 +2861,7 @@ Some configuration options can be set using Environment Variables: for use by the bootm command. See also "bootm_size" environment variable. Address defined by "bootm_low" is also the base of the initial memory mapping for the Linux - kernel -- see the description of CFG_BOOTMAPSZ. + kernel -- see the description of CONFIG_SYS_BOOTMAPSZ. bootm_size - Memory range available for image processing in the bootm command can be restricted. This variable is given as @@ -2909,7 +2909,7 @@ Some configuration options can be set using Environment Variables: is usually what you want since it allows for maximum initrd size. If for some reason you want to make sure that the initrd image is loaded below the - CFG_BOOTMAPSZ limit, you can set this environment + CONFIG_SYS_BOOTMAPSZ limit, you can set this environment variable to a value of "no" or "off" or "0". Alternatively, you can set it to a maximum upper address to use (U-Boot will still check that it @@ -3183,7 +3183,7 @@ Just make sure your machine specific header file (for instance include/asm-ppc/tqm8xx.h) includes the same definition of the Board Information structure as we define in include/asm-<arch>/u-boot.h, and make sure that your definition of IMAP_ADDR uses the same value -as your U-Boot configuration in CFG_IMMR. +as your U-Boot configuration in CONFIG_SYS_IMMR. Configuring the Linux kernel: @@ -3730,7 +3730,7 @@ locked as (mis-) used as memory, etc. cause you grief during the initial boot! It is frequently not used. - CFG_INIT_RAM_ADDR should be somewhere that won't interfere + CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere with your processor/board/system design. The default value you will find in any recent u-boot distribution in walnut.h should work for you. I'd set it to a value larger @@ -3827,7 +3827,7 @@ U-Boot is installed in the first 128 kB of the first Flash bank (on TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After booting and sizing and initializing DRAM, the code relocates itself to the upper end of DRAM. Immediately below the U-Boot code some -memory is reserved for use by malloc() [see CFG_MALLOC_LEN +memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN configuration setting]. Below that, a structure with global Board Info data is placed, followed by the stack (growing downward). diff --git a/README.nios_CONFIG_SYS_NIOS_CPU b/README.nios_CONFIG_SYS_NIOS_CPU new file mode 100644 index 0000000000..3547c343bd --- /dev/null +++ b/README.nios_CONFIG_SYS_NIOS_CPU @@ -0,0 +1,140 @@ + +=============================================================================== + C F G _ N I O S _ C P U _ * v s . N I O S S D K +=============================================================================== + +When ever you have to make a new NIOS CPU configuration you can use this table +as a reference list to the original NIOS SDK symbols made by Alteras SOPC +Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc. +Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description +(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO. + +C O R E N I O S S D K [1],[7] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_CLK nasys_clock_freq +CONFIG_SYS_NIOS_CPU_ICACHE nasys_icache_size +CONFIG_SYS_NIOS_CPU_DCACHE nasys_dcache_size +CONFIG_SYS_NIOS_CPU_REG_NUMS nasys_nios_num_regs +CONFIG_SYS_NIOS_CPU_MUL __nios_use_multiply__ +CONFIG_SYS_NIOS_CPU_MSTEP __nios_use_mstep__ +CONFIG_SYS_NIOS_CPU_STACK nasys_stack_top +CONFIG_SYS_NIOS_CPU_VEC_BASE nasys_vector_table +CONFIG_SYS_NIOS_CPU_VEC_SIZE nasys_vector_table_size +CONFIG_SYS_NIOS_CPU_VEC_NUMS +CONFIG_SYS_NIOS_CPU_RST_VECT nasys_reset_address +CONFIG_SYS_NIOS_CPU_DBG_CORE nasys_debug_core +CONFIG_SYS_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes +CONFIG_SYS_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size +CONFIG_SYS_NIOS_CPU_ROM_BASE na_boot_monitor_rom +CONFIG_SYS_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size +CONFIG_SYS_NIOS_CPU_OCI_BASE nasys_oci_core +CONFIG_SYS_NIOS_CPU_OCI_SIZE +CONFIG_SYS_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem + nasys_data_mem +CONFIG_SYS_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size + nasys_data_mem_size +CONFIG_SYS_NIOS_CPU_SDRAM_BASE na_sdram +CONFIG_SYS_NIOS_CPU_SDRAM_SIZE na_sdram_size +CONFIG_SYS_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash + nasys_am29lv065d_flash_0 + nasys_flash_0 +CONFIG_SYS_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size + +T I M E R N I O S S D K [3] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_TIMER_NUMS nasys_timer_count +CONFIG_SYS_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9] +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER [ptf]:period + [ptf]:period_units + [ptf]:mult +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot + +U A R T N I O S S D K [2] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_UART_NUMS nasys_uart_count +CONFIG_SYS_NIOS_CPU_UART[0-9] nasys_uart_[0-9] +CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq +CONFIG_SYS_NIOS_CPU_UART[0-9]_BR [ptf]:baud +CONFIG_SYS_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits +CONFIG_SYS_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits +CONFIG_SYS_NIOS_CPU_UART[0-9]_PA [ptf]:parity +CONFIG_SYS_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts +CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register + +P I O N I O S S D K [4] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_PIO_NUMS nasys_pio_count +CONFIG_SYS_NIOS_CPU_PIO[0-9] nasys_pio_[0-9] +CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq +CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width +CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri + [ptf]:has_out + [ptf]:has_in +CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture +CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type +CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type + +S P I N I O S S D K [6] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_SPI_NUMS nasys_spi_count +CONFIG_SYS_NIOS_CPU_SPI[0-9] nasys_spi_[0-9] +CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq +CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits +CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster +CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves +CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock +CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay +CONFIG_SYS_NIOS_CPU_SPI[0-9]_* [ptf]:* + +I D E N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_IDE_NUMS nasys_usersocket_count +CONFIG_SYS_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9] + +A S M I N I O S S D K [5] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_ASMI_NUMS nasys_asmi_count +CONFIG_SYS_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9] +CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq + +E t h e r n e t ( L A N ) N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_LAN_NUMS +CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE na_lan91c111 +CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET +CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq +CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH +CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE + +s y s t e m c o m p o s i n g N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_TICK_TIMER (na_low_priority_timer2) +CONFIG_SYS_NIOS_CPU_USER_TIMER (na_timer1) +CONFIG_SYS_NIOS_CPU_BUTTON_PIO (na_button_pio) +CONFIG_SYS_NIOS_CPU_LCD_PIO (na_lcd_pio) +CONFIG_SYS_NIOS_CPU_LED_PIO (na_led_pio) +CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio) +CONFIG_SYS_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio) +CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio) +CONFIG_SYS_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio) +CONFIG_SYS_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio) +CONFIG_SYS_NIOS_CPU_USER_SPI (na_spi) + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/ds/ds_nioscpu.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf +[6] http://www.altera.com/literature/ds/ds_nios_spi.pdf +[7] http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf + + +=============================================================================== +Stephan Linz <linz@li-pro.net> diff --git a/api/api_storage.c b/api/api_storage.c index 5642dd33bc..6fac98bffd 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -67,28 +67,28 @@ static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, }; void dev_stor_init(void) { #if defined(CONFIG_CMD_IDE) - specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE; + specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE; specs[ENUM_IDE].enum_started = 0; specs[ENUM_IDE].enum_ended = 0; specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE; specs[ENUM_IDE].name = "ide"; #endif #if defined(CONFIG_CMD_MMC) - specs[ENUM_MMC].max_dev = CFG_MMC_MAX_DEVICE; + specs[ENUM_MMC].max_dev = CONFIG_SYS_MMC_MAX_DEVICE; specs[ENUM_MMC].enum_started = 0; specs[ENUM_MMC].enum_ended = 0; specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC; specs[ENUM_MMC].name = "mmc"; #endif #if defined(CONFIG_CMD_SATA) - specs[ENUM_SATA].max_dev = CFG_SATA_MAX_DEVICE; + specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE; specs[ENUM_SATA].enum_started = 0; specs[ENUM_SATA].enum_ended = 0; specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA; specs[ENUM_SATA].name = "sata"; #endif #if defined(CONFIG_CMD_SCSI) - specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE; + specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE; specs[ENUM_SCSI].enum_started = 0; specs[ENUM_SCSI].enum_ended = 0; specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI; diff --git a/board/AtmarkTechno/suzaku/flash.c b/board/AtmarkTechno/suzaku/flash.c index 49a06733a5..ce6fae01b4 100644 --- a/board/AtmarkTechno/suzaku/flash.c +++ b/board/AtmarkTechno/suzaku/flash.c @@ -24,7 +24,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned long flash_init(void) { diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c index 39c97b1f53..d509a8fdbc 100644 --- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c +++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c @@ -32,7 +32,7 @@ int checkboard (void) { puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n"); -#if (TEXT_BASE == CFG_INT_FLASH_BASE) +#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) puts (" Boot from Internal FLASH\n"); #endif @@ -45,10 +45,10 @@ phys_size_t initdram (int board_type) size = 0; MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 - | MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4); -#ifdef CFG_SDRAM_BASE0 + | MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4); +#ifdef CONFIG_SYS_SDRAM_BASE0 - MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0) + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) | MCFSDRAMC_DACR_PS_16; @@ -57,17 +57,17 @@ phys_size_t initdram (int board_type) MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; - *(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5; + *(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5; MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; for (i = 0; i < 2000; i++) asm (" nop"); mbar_writeLong (MCFSDRAMC_DACR0, mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS); - *(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5; - size += CFG_SDRAM_SIZE * 1024 * 1024; + *(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5; + size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; #endif -#ifdef CFG_SDRAM_BASE1 - MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1) +#ifdef CONFIG_SYS_SDRAM_BASE1 + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) | MCFSDRAMC_DACR_PS_16; @@ -76,25 +76,25 @@ phys_size_t initdram (int board_type) MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; - *(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5; + *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5; MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; for (i = 0; i < 2000; i++) asm (" nop"); MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; - *(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5; - size += CFG_SDRAM_SIZE1 * 1024 * 1024; + *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; + size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024; #endif return size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); diff --git a/board/BuS/EB+MCF-EV123/VCxK.c b/board/BuS/EB+MCF-EV123/VCxK.c index 4b46b7c9a5..f2fe353dbe 100644 --- a/board/BuS/EB+MCF-EV123/VCxK.c +++ b/board/BuS/EB+MCF-EV123/VCxK.c @@ -25,7 +25,7 @@ #include <asm/m5282.h> #include "VCxK.h" -vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE); +vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE); #define VCXK_BWS vcxk_bws static ulong vcxk_driver; diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.c b/board/BuS/EB+MCF-EV123/cfm_flash.c index 98e563fc5c..fe03b17581 100644 --- a/board/BuS/EB+MCF-EV123/cfm_flash.c +++ b/board/BuS/EB+MCF-EV123/cfm_flash.c @@ -28,14 +28,14 @@ #if defined(CONFIG_M5281) || defined(CONFIG_M5282) -#if (CFG_CLK>20000000) - #define CFM_CLK (((long) CFG_CLK / (400000 * 8) + 1) | 0x40) +#if (CONFIG_SYS_CLK>20000000) + #define CFM_CLK (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40) #else - #define CFM_CLK ((long) CFG_CLK / 400000 + 1) + #define CFM_CLK ((long) CONFIG_SYS_CLK / 400000 + 1) #endif #define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \ - (CFG_MBAR & 0xC0000000)) + (CONFIG_SYS_MBAR & 0xC0000000)) void cfm_flash_print_info (flash_info_t * info) { @@ -60,8 +60,8 @@ void cfm_flash_init (flash_info_t * info) MCFCFM_MCR = 0; MCFCFM_CLKD = CFM_CLK; debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\ - CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ - CFG_CLK); + CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ + CONFIG_SYS_CLK); MCFCFM_SACC = 0; MCFCFM_DACC = 0; @@ -86,7 +86,7 @@ void cfm_flash_init (flash_info_t * info) { if (sector == 0) { - info->start[sector] = CFG_INT_FLASH_BASE; + info->start[sector] = CONFIG_SYS_INT_FLASH_BASE; } else { @@ -187,7 +187,7 @@ int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cn return rc; } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION int cfm_flash_protect(flash_info_t * info,long sector,int prot) { diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.h b/board/BuS/EB+MCF-EV123/cfm_flash.h index cc8cdbd1eb..ed4e7943e7 100644 --- a/board/BuS/EB+MCF-EV123/cfm_flash.h +++ b/board/BuS/EB+MCF-EV123/cfm_flash.h @@ -33,7 +33,7 @@ extern void cfm_flash_print_info (flash_info_t * info); extern int cfm_flash_erase_sector (flash_info_t * info, int sector); extern void cfm_flash_init (flash_info_t * info); extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION extern int cfm_flash_protect(flash_info_t * info,long sector,int prot); #endif diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c index c2a1b6ff62..3c36367d74 100644 --- a/board/BuS/EB+MCF-EV123/flash.c +++ b/board/BuS/EB+MCF-EV123/flash.c @@ -27,10 +27,10 @@ #include <common.h> #include "cfm_flash.h" -#define PHYS_FLASH_1 CFG_FLASH_BASE +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x200000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; void flash_print_info (flash_info_t * info) { @@ -83,7 +83,7 @@ unsigned long flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; switch (i) @@ -93,8 +93,8 @@ unsigned long flash_init (void) (AMD_MANUFACT & FLASH_VENDMASK) | (AMD_ID_LV160B & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); flashbase = PHYS_FLASH_1; for (j = 0; j < flash_info[i].sector_count; j++) { if (j == 0) { @@ -128,8 +128,8 @@ unsigned long flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0xffff, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]); return size; } @@ -177,7 +177,7 @@ int amd_flash_erase_sector(flash_info_t * info, int sector) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; state = ERR_TIMOUT; } @@ -303,7 +303,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { state = ERR_TIMOUT; } if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK))) @@ -390,7 +390,7 @@ int amd_flash_protect(flash_info_t * info,long sector,int prot) return rc; } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION int flash_real_protect(flash_info_t * info,long sector,int prot) { diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c index 8ae2ec69ce..7f925142c9 100644 --- a/board/BuS/EB+MCF-EV123/mii.c +++ b/board/BuS/EB+MCF-EV123/mii.c @@ -38,15 +38,15 @@ int fecpin_setclear(struct eth_device *dev, int setclear) { if (setclear) { MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CFG_PEHLPAR; + MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; } else { MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; + MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; } return 0; } -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII) #include <miiphy.h> /* Make MII read/write commands for the FEC. */ @@ -132,9 +132,9 @@ uint mii_send(uint mii_cmd) return (mii_reply & 0xffff); /* data read from phy */ } -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ +#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */ -#if defined(CFG_DISCOVER_PHY) +#if defined(CONFIG_SYS_DISCOVER_PHY) int mii_discover_phy(struct eth_device *dev) { #define MAX_PHY_PASSES 11 @@ -199,7 +199,7 @@ int mii_discover_phy(struct eth_device *dev) return phyaddr; } -#endif /* CFG_DISCOVER_PHY */ +#endif /* CONFIG_SYS_DISCOVER_PHY */ void mii_init(void) __attribute__((weak,alias("__mii_init"))); diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c index 5f506314c5..905df92b1d 100644 --- a/board/LEOX/elpt860/elpt860.c +++ b/board/LEOX/elpt860/elpt860.c @@ -138,23 +138,23 @@ const uint sdram_table[] = { /* ------------------------------------------------------------------------- */ -#define CFG_PC4 0x0800 +#define CONFIG_SYS_PC4 0x0800 -#define CFG_DS1 CFG_PC4 +#define CONFIG_SYS_DS1 CONFIG_SYS_PC4 /* * Very early board init code (fpga boot, etc.) */ int board_early_init_f (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* * Light up the red led on ELPT860 pcb (DS1) (PCDAT) */ - immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */ - immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */ - immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */ + immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1; /* PCDAT (DS1 = 0) */ + immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1; /* PCPAR (0=general purpose I/O) */ + immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1; /* PCDIR (I/O: 0=input, 1=output) */ return (0); /* success */ } @@ -181,7 +181,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size_b0 = 0; @@ -207,7 +207,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; /* * The following value is used as an address (i.e. opcode) for @@ -229,10 +229,10 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -252,7 +252,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -260,7 +260,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -269,7 +269,7 @@ phys_size_t initdram (int board_type) } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -282,22 +282,22 @@ phys_size_t initdram (int board_type) */ if (size_b0 < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } /* * Final mapping: map bigger bank first */ - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; { unsigned long reg; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } @@ -319,7 +319,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -329,20 +329,20 @@ dram_size (long int mamr_value, long int *base, long int maxsize) /* ------------------------------------------------------------------------- */ -#define CFG_PA1 0x4000 -#define CFG_PA2 0x2000 +#define CONFIG_SYS_PA1 0x4000 +#define CONFIG_SYS_PA2 0x2000 -#define CFG_LBKs (CFG_PA2 | CFG_PA1) +#define CONFIG_SYS_LBKs (CONFIG_SYS_PA2 | CONFIG_SYS_PA1) void reset_phy (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect * and no AUI loopback */ - immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */ - immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */ - immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */ + immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs; /* PADAT (LBK eth 1&2 = 0) */ + immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs; /* PAPAR (0=general purpose I/O) */ + immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs; /* PADIR (I/O: 0=input, 1=output) */ } diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c index 668aee2f84..9a75aad18d 100644 --- a/board/LEOX/elpt860/flash.c +++ b/board/LEOX/elpt860/flash.c @@ -33,7 +33,7 @@ /* ** Note 1: In this file, you have to provide the following variable: ** ------ -** flash_info_t flash_info[CFG_MAX_FLASH_BANKS] +** flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS] ** 'flash_info_t' structure is defined into 'include/flash.h' ** and defined as extern into 'common/cmd_flash.c' ** @@ -62,10 +62,10 @@ #ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET) +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Internal Functions @@ -82,13 +82,13 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -105,20 +105,20 @@ flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE, + size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1, &flash_info[0]); #endif @@ -383,7 +383,7 @@ flash_erase (flash_info_t *info, addr = (volatile unsigned char *)(info->start[l_sect]); while ( (addr[0] & 0x80) != 0x80 ) { - if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT ) + if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT ) { printf ("Timeout\n"); return ( 1 ); @@ -556,7 +556,7 @@ write_word (flash_info_t *info, start = get_timer (0); while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) ) { - if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) + if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { return (1); } @@ -602,7 +602,7 @@ write_byte (flash_info_t *info, start = get_timer (0); while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) ) { - if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) + if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { return (1); } diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c index 40c951d068..949af18025 100644 --- a/board/MAI/AmigaOneG3SE/cmd_boota.c +++ b/board/MAI/AmigaOneG3SE/cmd_boota.c @@ -27,7 +27,7 @@ struct bootcode_block bblk; int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR; + unsigned char *load_address = (unsigned char *) CONFIG_SYS_LOAD_ADDR; unsigned char *base_address; unsigned long offset; diff --git a/board/MAI/AmigaOneG3SE/flash.c b/board/MAI/AmigaOneG3SE/flash.c index 409b955fd5..a96d5bae29 100644 --- a/board/MAI/AmigaOneG3SE/flash.c +++ b/board/MAI/AmigaOneG3SE/flash.c @@ -1,14 +1,14 @@ #include <common.h> #include <flash.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned long flash_init(void) { int i; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = 0; diff --git a/board/MAI/AmigaOneG3SE/flash_new.c b/board/MAI/AmigaOneG3SE/flash_new.c index 3efee7e98e..7b7ea1697a 100644 --- a/board/MAI/AmigaOneG3SE/flash_new.c +++ b/board/MAI/AmigaOneG3SE/flash_new.c @@ -39,7 +39,7 @@ #endif /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static ulong flash_get_size (ulong addr, flash_info_t *info); static int flash_get_offsets (ulong base, flash_info_t *info); @@ -80,7 +80,7 @@ unsigned long flash_init_old(void) { int i; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = 0; @@ -101,25 +101,25 @@ unsigned long flash_init (void) flash_to_xd(); /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = 0; flash_info[i].size = 0; } - DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE); + DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE); - flash_size = flash_get_size (CFG_FLASH_BASE, flash_info); + flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info); DEBUGF("## Flash bank size: %08lx\n", flash_size); if (flash_size) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \ - CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \ + CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif @@ -286,10 +286,10 @@ static ulong flash_get_size (ulong addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } if (! flash_get_offsets (addr, info)) { @@ -418,10 +418,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = info->start[l_sect]; - DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); + DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT); while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); flash_reset (info->start[0]); flash_to_mem(); @@ -562,7 +562,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { flash_reset (addr); flash_to_mem(); return (1); diff --git a/board/MAI/AmigaOneG3SE/i8259.h b/board/MAI/AmigaOneG3SE/i8259.h index 05c40522d1..eb08e13d43 100644 --- a/board/MAI/AmigaOneG3SE/i8259.h +++ b/board/MAI/AmigaOneG3SE/i8259.h @@ -21,20 +21,20 @@ * MA 02111-1307 USA */ -#define ICW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1 -#define ICW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1 -#define ICW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2 -#define ICW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2 -#define ICW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3 -#define ICW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3 -#define ICW4_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4 -#define ICW4_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4 -#define OCW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1 -#define OCW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1 -#define OCW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2 -#define OCW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2 -#define OCW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3 -#define OCW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3 +#define ICW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1 +#define ICW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1 +#define ICW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2 +#define ICW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2 +#define ICW3_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3 +#define ICW3_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3 +#define ICW4_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4 +#define ICW4_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4 +#define OCW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1 +#define OCW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1 +#define OCW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2 +#define OCW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2 +#define OCW3_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3 +#define OCW3_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3 #define IMR_1 OCW1_1 #define IMR_2 OCW1_2 diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c index 86b44150d5..de46d6e37e 100644 --- a/board/MAI/AmigaOneG3SE/interrupts.c +++ b/board/MAI/AmigaOneG3SE/interrupts.c @@ -119,12 +119,12 @@ int interrupt_init (void) #ifdef DEBUG puts("interrupt_init: setting decrementer_count\n"); #endif - decrementer_count = get_tbclk() / CFG_HZ; + decrementer_count = get_tbclk() / CONFIG_SYS_HZ; #ifdef DEBUG puts("interrupt_init: setting actual decremter\n"); #endif - set_dec (get_tbclk() / CFG_HZ); + set_dec (get_tbclk() / CONFIG_SYS_HZ); #ifdef DEBUG puts("interrupt_init: clearing external interrupt table\n"); diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c index 724a44db7d..a297005ed2 100644 --- a/board/MAI/AmigaOneG3SE/ps2kbd.c +++ b/board/MAI/AmigaOneG3SE/ps2kbd.c @@ -214,7 +214,7 @@ int isa_kbd_init (void) } } -#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE extern int overwrite_console (void); #else int overwrite_console (void) @@ -492,22 +492,22 @@ unsigned char handle_kbd_event (void) */ unsigned char kbd_read_status(void) { - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); + return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); } unsigned char kbd_read_input(void) { - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); + return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); } void kbd_write_command(unsigned char cmd) { - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); } void kbd_write_output(unsigned char data) { - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); } int kbd_read_data(void) diff --git a/board/MAI/AmigaOneG3SE/serial.c b/board/MAI/AmigaOneG3SE/serial.c index b6f57c7246..88039f3d00 100644 --- a/board/MAI/AmigaOneG3SE/serial.c +++ b/board/MAI/AmigaOneG3SE/serial.c @@ -6,7 +6,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_NS16550 +#ifndef CONFIG_SYS_NS16550 static uint32 ComPort1; uint16 SerialEcho = 1; @@ -147,8 +147,8 @@ void serial_debug_putc (int c) #else -const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1; -const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2; +const NS16550_t Com0 = (NS16550_t) CONFIG_SYS_NS16550_COM1; +const NS16550_t Com1 = (NS16550_t) CONFIG_SYS_NS16550_COM2; int serial_init (void) { diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c index 26cdcdf760..6d1133f84e 100644 --- a/board/MAI/AmigaOneG3SE/usb_uhci.c +++ b/board/MAI/AmigaOneG3SE/usb_uhci.c @@ -627,7 +627,7 @@ int usb_lowlevel_init(void) pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); usb_base_addr&=0xFFFFFFF0; - usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS; + usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS; rh.devnum = 0; usb_init_skel(); reset_hc(); diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c index 3603372d07..21eae0e949 100644 --- a/board/Marvell/common/flash.c +++ b/board/Marvell/common/flash.c @@ -48,7 +48,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last); int write_word_intel (bank_addr_t addr, bank_word_t value); -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -68,14 +68,14 @@ unsigned long flash_init (void) unsigned long base, flash_size; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* the boot flash */ - base = CFG_FLASH_BASE; + base = CONFIG_SYS_FLASH_BASE; size_b0 = - flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base, + flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base, &flash_info[0]); printf ("[%ldkB@%lx] ", size_b0 / 1024, base); @@ -84,11 +84,11 @@ unsigned long flash_init (void) printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20); } - base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE); + base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE); /* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/ - for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { unsigned long size = - flash_get_size (CFG_EXTRA_FLASH_WIDTH, + flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *) base, &flash_info[i]); printf ("[%ldMB@%lx] ", size >> 20, base); @@ -617,7 +617,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* has the timeout limit been reached? */ if (get_timer (start) > - CFG_FLASH_ERASE_TOUT) + CONFIG_SYS_FLASH_ERASE_TOUT) { /* timeout limit reached */ printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]); @@ -776,7 +776,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) addr = (volatile unsigned char *) (info->start[l_sect]); /* broken for 2x16: TODO */ while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -956,7 +956,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) { /* has the timeout limit been reached? */ if (get_timer (start) > - CFG_FLASH_WRITE_TOUT) { + CONFIG_SYS_FLASH_WRITE_TOUT) { /* timeout limit reached */ printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data); /* reset the flash */ @@ -1064,7 +1064,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c index 32b2b30a4a..d426044392 100644 --- a/board/Marvell/common/i2c.c +++ b/board/Marvell/common/i2c.c @@ -48,7 +48,7 @@ static void i2c_init (int speed, int slaveaddr) unsigned int actualN = 0, actualM = 0; unsigned int control, status; unsigned int minMargin = 0xffffffff; - unsigned int tclk = CFG_TCLK; + unsigned int tclk = CONFIG_SYS_TCLK; unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ DP (puts ("i2c_init\n")); @@ -372,7 +372,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_read\n")); @@ -447,7 +447,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_write\n")); @@ -500,7 +500,7 @@ int i2c_probe (uchar chip) unsigned int i2c_status; #endif uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_probe\n")); diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c index d26f883ad3..42b3ee1548 100644 --- a/board/Marvell/common/intel_flash.c +++ b/board/Marvell/common/intel_flash.c @@ -152,7 +152,7 @@ int write_word_intel (bank_addr_t addr, bank_word_t value) /* data polling for D7 */ start = get_timer (0); do { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { retval = 1; goto done; } @@ -227,7 +227,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last) do { now = get_timer (start); - if (now - estart > CFG_FLASH_ERASE_TOUT) { + if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (sect %d)\n", sect); haderr = 1; break; diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h index 666a4cdcad..bd8941ea5f 100644 --- a/board/Marvell/common/intel_flash.h +++ b/board/Marvell/common/intel_flash.h @@ -68,7 +68,7 @@ /* ID and Lock Configuration */ #define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ #define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CFG_FLASH_ID +#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID /* dimensions */ #define CHIP_WIDTH 2 /* chips are in 16 bit mode */ diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S index 41c3a9508e..b3a089803a 100644 --- a/board/Marvell/common/misc.S +++ b/board/Marvell/common/misc.S @@ -16,7 +16,7 @@ board_relocate_rom: mflr r7 /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h + lis r11, CONFIG_SYS_GT_REGS@h /* if we're using ECC, we must use the DMA engine to copy ourselves */ bl start_idma_transfer_0 bl wait_for_idma_0 @@ -29,12 +29,12 @@ board_relocate_rom: board_init_ecc: mflr r7 /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ /* now that we're running from ram, init the rest of main memory * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l + lis r8, CONFIG_SYS_MONITOR_LEN@h + ori r8, r8, CONFIG_SYS_MONITOR_LEN@l divw r3, r10, r8 @@ -120,15 +120,15 @@ stop_idma_engine_0: blr #endif -#ifdef CFG_BOARD_ASM_INIT +#ifdef CONFIG_SYS_BOARD_ASM_INIT /* NOTE: trashes r3-r7 */ .globl board_asm_init board_asm_init: /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r3, CONFIG_SYS_DFL_GT_REGS@h + ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTERNAL_SPACE_DECODE /* test to see if we've already moved */ diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c index 475445b788..7fbf28a609 100644 --- a/board/Marvell/common/ns16550.c +++ b/board/Marvell/common/ns16550.c @@ -1,7 +1,7 @@ /* * COM1 NS16550 support * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines + * modified to use CONFIG_SYS_ISA_MEM and new defines * * further modified by Josh Huber <huber@mclx.com> to support * the DUART on the Galileo Eval board. (db64360) @@ -13,8 +13,8 @@ #ifdef ZUMA_NTL /* no 16550 device */ #else -const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0), - (NS16550_t) (CFG_DUART_IO + 0x20) +const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0), + (NS16550_t) (CONFIG_SYS_DUART_IO + 0x20) }; volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h index f2ed2abc9e..b9691ab5af 100644 --- a/board/Marvell/common/ns16550.h +++ b/board/Marvell/common/ns16550.h @@ -2,7 +2,7 @@ * NS16550 Serial Port * originally from linux source (arch/ppc/boot/ns16550.h) * modified slightly to - * have addresses as offsets from CFG_ISA_BASE + * have addresses as offsets from CONFIG_SYS_ISA_BASE * added a few more definitions * added prototypes for ns16550.c * reduced no of com ports to 2 diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 01efbea77b..3e7f406ffb 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -52,17 +52,17 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) int clock_divisor = 230400 / gd->baudrate; #endif mpsc_init (gd->baudrate); /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit (COM_PORTS[1], clock_divisor); #endif return (0); @@ -97,10 +97,10 @@ int serial_init (void) { int clock_divisor = 230400 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 (void) NS16550_init (0, clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 (void) NS16550_init (1, clock_divisor); #endif return (0); @@ -109,29 +109,29 @@ int serial_init (void) void serial_putc (const char c) { if (c == '\n') - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } int serial_getc (void) { - return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } int serial_tstc (void) { - return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } void serial_setbrg (void) { int clock_divisor = 230400 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit (COM_PORTS[1], clock_divisor); #endif } diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c index c03d03d387..35b695e862 100644 --- a/board/Marvell/db64360/db64360.c +++ b/board/Marvell/db64360/db64360.c @@ -55,7 +55,7 @@ /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -64,7 +64,7 @@ */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); /* ------------------------------------------------------------------------- */ @@ -127,7 +127,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ @@ -136,7 +136,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } /* Enable master */ @@ -154,21 +154,21 @@ static void gt_pci_config (void) /* ronen- add write to pci remap registers for 64460. in 64360 when writing to pci base go and overide remap automaticaly, in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); /* PCI interface settings */ /* Timeout set to retry forever */ @@ -184,7 +184,7 @@ static void gt_pci_config (void) for (stat = 0; stat <= PCI_HOST1; stat++) pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); + SELF, CONFIG_SYS_GT_REGS); #endif } @@ -200,7 +200,7 @@ static void gt_cpu_config (void) tmp = GTREGREAD (CPU_CONFIGURATION); /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ +#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ tmp |= CPU_CONF_SINGLE_CPU; #endif @@ -251,7 +251,7 @@ int board_early_init_f (void) * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); /* No PCI in first release of Port To_do: enable it. */ #ifdef CONFIG_PCI @@ -297,56 +297,56 @@ int board_early_init_f (void) * on-board sram on the eval board, and updates the correct * registers to boot from the sram. (device0) */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) sram_boot = 1; if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); /* configure device timing */ -#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ +#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); #endif -#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); #endif -#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); #endif -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ +#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ /* detect if we are booting from the 32 bit flash */ if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); + CONFIG_SYS_32BIT_BOOT_PAR); } else { /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); } #else /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ #endif gt_cpu_config (); /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); DEBUG_LED0_ON (); DEBUG_LED1_ON (); DEBUG_LED2_ON (); @@ -359,7 +359,7 @@ int board_early_init_f (void) int misc_init_r () { icache_enable (); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif #ifdef CONFIG_MPSC @@ -380,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd) /* check to see if we booted from the sram. If so, move things * back to the way they should be. (we're running from main * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); } display_mem_map (); /* now, jump to the main ppcboot board init code */ @@ -402,7 +402,7 @@ int checkboard (void) { int l_type = 0; - printf ("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); return (l_type); } @@ -415,34 +415,34 @@ void debug_led (int led, int mode) if (mode == 1) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x08000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x0c000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x10000); break; } } else if (mode == 0) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x14000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x18000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x1c000); break; } @@ -513,7 +513,7 @@ int display_mem_map (void) /* DRAM check routines copied from gw8260 */ -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ @@ -544,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaULL, @@ -607,7 +607,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -634,9 +634,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -661,8 +661,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; + const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; unsigned int i; /* write address to each location */ @@ -679,9 +679,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -739,7 +739,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -771,8 +771,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; + const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; unsigned int i; @@ -848,9 +848,9 @@ int testdram (void) /* runwalk = 0; */ if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); } -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { printf ("Test DATA ... "); if (mem_test_data () == 1) { @@ -860,7 +860,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { @@ -870,7 +870,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { printf ("Test WALKING ONEs ... "); if (mem_test_walk () == 1) { @@ -886,7 +886,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ @@ -925,7 +925,7 @@ void board_prebootm_init () /* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */ /* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); + my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); icache_disable (); dcache_disable (); diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c index 923d95555b..7ad6ae8c0e 100644 --- a/board/Marvell/db64360/mpsc.c +++ b/board/Marvell/db64360/mpsc.c @@ -426,7 +426,7 @@ void mpsc_sdma_init (void) (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); /* no high address remap*/ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); @@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate) #ifdef ZUMA_NTL /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #else - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #endif galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c index 5637284124..a7e3c95b8c 100644 --- a/board/Marvell/db64360/pci.c +++ b/board/Marvell/db64360/pci.c @@ -859,14 +859,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -901,14 +901,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index ecadaf2710..d0817d7e20 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -312,7 +312,7 @@ return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT +#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT for (i = 0; i <= 127; i++) { printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], @@ -690,16 +690,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP < - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP < - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { dimmInfo-> maxClSupported_DDR @@ -714,16 +714,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP > - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP > - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { printf ("*********************************************************\n"); printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); @@ -1290,37 +1290,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) case 0x0: case 0x80: /* refresh period is 15.625 usec */ sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) + (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x1: case 0x81: /* refresh period is 3.9 usec */ sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x2: case 0x82: /* refresh period is 7.8 usec */ sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x3: case 0x83: /* refresh period is 31.3 usec */ sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x4: case 0x84: /* refresh period is 62.5 usec */ sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x5: case 0x85: /* refresh period is 125 usec */ sdram_config_reg = - (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; default: /* refresh period undefined */ @@ -1807,7 +1807,7 @@ phys_size_t initdram (int board_type) printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { /* skip over banks that are not populated */ if (!checkbank[bank_no]) continue; diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c index 8a05cd2098..14e635592e 100644 --- a/board/Marvell/db64460/db64460.c +++ b/board/Marvell/db64460/db64460.c @@ -55,7 +55,7 @@ /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -64,7 +64,7 @@ */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); /* ------------------------------------------------------------------------- */ @@ -127,7 +127,7 @@ static void gt_pci_confi |