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authorThierry Reding <treding@nvidia.com>2015-07-27 11:45:26 -0600
committerTom Warren <twarren@nvidia.com>2015-07-28 10:30:18 -0700
commit6527268d6e8628cd121376fd0ceed2be81ebd64f (patch)
tree8f5aa045891fbea206363b859f7c204b6074198b
parent32b3234f09bc4d1e60f4972cc2ecbbf807e228dc (diff)
downloadtalos-obmc-uboot-6527268d6e8628cd121376fd0ceed2be81ebd64f.tar.gz
talos-obmc-uboot-6527268d6e8628cd121376fd0ceed2be81ebd64f.zip
ARM: tegra: Disable SPL and non-cached memory on 64-bit
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in AArch64 mode so that we don't need the SPL. Non-cached memory is not implemented (yet) for 64-bit ARM. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r--include/configs/tegra-common.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 7b4c0d7063..49fa8b3210 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -43,7 +43,9 @@
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
#endif
+#ifndef CONFIG_ARM64
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+#endif
/*
* NS16550 Configuration
@@ -101,9 +103,11 @@
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
+#ifndef CONFIG_ARM64
#ifndef CONFIG_SPL_BUILD
#define CONFIG_USE_ARCH_MEMCPY
#endif
+#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
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