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authorAndrey Skvortsov <andrej.skvortzov@gmail.com>2015-12-20 21:09:58 +0300
committerStefano Babic <sbabic@denx.de>2016-01-07 17:54:53 +0100
commit587c3f8ebe356b558f1876414885c1b4a31294ab (patch)
tree6194dc359a4751eceeb4eae8df9d73c9ce9cab83
parent88f91d1375aaf4d21d77a2f2daa351dea9132a58 (diff)
downloadtalos-obmc-uboot-587c3f8ebe356b558f1876414885c1b4a31294ab.tar.gz
talos-obmc-uboot-587c3f8ebe356b558f1876414885c1b4a31294ab.zip
imx_watchdog: always set minimal timeout in reset_cpu
The problem is that timeout bits in WCR register were leaved unchanged. So previously set timeout value was applied and therefore 'reset' command takes any value up to two minutes, depending on previous watchdog settings, instead of minimal 0.5 seconds. Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
-rw-r--r--drivers/watchdog/imx_watchdog.c2
-rw-r--r--include/fsl_wdog.h1
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 0d775956bf..f9f817596f 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -43,7 +43,7 @@ void reset_cpu(ulong addr)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- clrsetbits_le16(&wdog->wcr, 0, WCR_WDE);
+ clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
writew(0x5555, &wdog->wsr);
writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h
index d15a70cedb..f698d4d64e 100644
--- a/include/fsl_wdog.h
+++ b/include/fsl_wdog.h
@@ -16,3 +16,4 @@ struct watchdog_regs {
#define WCR_WDT 0x08
#define WCR_SRS 0x10
#define SET_WCR_WT(x) (x << 8)
+#define WCR_WT_MSK SET_WCR_WT(0xFF)
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