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authorYork Sun <york.sun@nxp.com>2016-05-18 21:11:19 -0700
committerYork Sun <york.sun@nxp.com>2016-06-03 14:12:06 -0700
commit5605dc6135f6f26560ef3b0c6ebc5141c531179a (patch)
tree261ba20afcda83bd9e50ea82f9981eac9b151752
parentc4f97b1f53a48ab52efc221b73a235797375fbfb (diff)
downloadtalos-obmc-uboot-5605dc6135f6f26560ef3b0c6ebc5141c531179a.tar.gz
talos-obmc-uboot-5605dc6135f6f26560ef3b0c6ebc5141c531179a.zip
drivers/ddr/fsl: Fix timing_cfg_2 register
Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far. Signed-off-by: York Sun <york.sun@nxp.com>
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index b26269c14d..1d5cec662c 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
| ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23)
| ((wr_lat & 0xf) << 19)
- | ((wr_lat & 0x10) << 14)
+ | ((wr_lat & 0x10) << 18)
| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
| ((cke_pls & 0x7) << 6)
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