ARM: uniphier: merge DDR PHY init code for 3 SoCs

Now these three are almost the same.  The only difference is the DTPR1
register dependency on the DRAM size, but it can be ignored.  (It has
already been ignored in PH1-sLD8 and PH1-Pro4.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

7 files changed, 14 insertions, 167 deletions

diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index a0a6003065..3d1553cbe1 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -7,9 +7,9 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= umc-ph1-ld4.o \
 					   ddrphy-training.o ddrphy-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= umc-ph1-pro4.o \
-					   ddrphy-training.o ddrphy-ph1-pro4.o
+					   ddrphy-training.o ddrphy-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= umc-ph1-sld8.o \
-					   ddrphy-training.o ddrphy-ph1-sld8.o
+					   ddrphy-training.o ddrphy-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= umc-proxstream2.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= umc-proxstream2.o
 
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
index 3000a284bb..27be1cc21e 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
@@ -41,18 +41,12 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
 	writel(0x0000040B, &phy->dcr);
 	if (freq == 1333) {
 		writel(0x85589955, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a8253c0, &phy->dtpr[1]);
-		else
-			writel(0x1a8363c0, &phy->dtpr[1]);
+		writel(0x1a8363c0, &phy->dtpr[1]);
 		writel(0x5002c200, &phy->dtpr[2]);
 		writel(0x00000b51, &phy->mr0);
 	} else {
 		writel(0x999cbb66, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a82dbc0, &phy->dtpr[1]);
-		else
-			writel(0x1a878400, &phy->dtpr[1]);
+		writel(0x1a878400, &phy->dtpr[1]);
 		writel(0xa00214f8, &phy->dtpr[2]);
 		writel(0x00000d71, &phy->mr0);
 	}
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
deleted file mode 100644
index b4dca3596f..0000000000
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include "ddrphy-regs.h"
-
-int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
-			 bool ddr3plus)
-{
-	u32 tmp;
-
-	writel(0x0300c473, &phy->pgcr[1]);
-	if (freq == 1333) {
-		writel(0x0a806844, &phy->ptr[0]);
-		writel(0x208e0124, &phy->ptr[1]);
-	} else {
-		writel(0x0c807d04, &phy->ptr[0]);
-		writel(0x2710015E, &phy->ptr[1]);
-	}
-	writel(0x00083DEF, &phy->ptr[2]);
-	if (freq == 1333) {
-		writel(0x0f051616, &phy->ptr[3]);
-		writel(0x06ae08d6, &phy->ptr[4]);
-	} else {
-		writel(0x12061A80, &phy->ptr[3]);
-		writel(0x08027100, &phy->ptr[4]);
-	}
-	writel(0xF004001A, &phy->dsgcr);
-
-	/* change the value of the on-die pull-up/pull-down registors */
-	tmp = readl(&phy->dxccr);
-	tmp &= ~0x0ee0;
-	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
-	writel(tmp, &phy->dxccr);
-
-	writel(0x0000040B, &phy->dcr);
-	if (freq == 1333) {
-		writel(0x85589955, &phy->dtpr[0]);
-		writel(0x1a8363c0, &phy->dtpr[1]);
-		writel(0x5002c200, &phy->dtpr[2]);
-		writel(0x00000b51, &phy->mr0);
-	} else {
-		writel(0x999cbb66, &phy->dtpr[0]);
-		writel(0x1a878400, &phy->dtpr[1]);
-		writel(0xa00214f8, &phy->dtpr[2]);
-		writel(0x00000d71, &phy->mr0);
-	}
-	writel(0x00000006, &phy->mr1);
-	if (freq == 1333)
-		writel(0x00000290, &phy->mr2);
-	else
-		writel(0x00000298, &phy->mr2);
-
-	writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
-
-	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
-		;
-
-	writel(0x0300C473, &phy->pgcr[1]);
-	writel(0x0000005D, &phy->zq[0].cr[1]);
-
-	return 0;
-}
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
deleted file mode 100644
index 0d2ae42685..0000000000
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include "ddrphy-regs.h"
-
-int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
-			 bool ddr3plus)
-{
-	u32 tmp;
-
-	writel(0x0300c473, &phy->pgcr[1]);
-	if (freq == 1333) {
-		writel(0x0a806844, &phy->ptr[0]);
-		writel(0x208e0124, &phy->ptr[1]);
-	} else {
-		writel(0x0c807d04, &phy->ptr[0]);
-		writel(0x2710015E, &phy->ptr[1]);
-	}
-	writel(0x00083DEF, &phy->ptr[2]);
-	if (freq == 1333) {
-		writel(0x0f051616, &phy->ptr[3]);
-		writel(0x06ae08d6, &phy->ptr[4]);
-	} else {
-		writel(0x12061A80, &phy->ptr[3]);
-		writel(0x08027100, &phy->ptr[4]);
-	}
-	writel(0xF004001A, &phy->dsgcr);
-
-	/* change the value of the on-die pull-up/pull-down registors */
-	tmp = readl(&phy->dxccr);
-	tmp &= ~0x0ee0;
-	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
-	writel(tmp, &phy->dxccr);
-
-	writel(0x0000040B, &phy->dcr);
-	if (freq == 1333) {
-		writel(0x85589955, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a8363c0, &phy->dtpr[1]);
-		else
-			writel(0x1a8363c0, &phy->dtpr[1]);
-		writel(0x5002c200, &phy->dtpr[2]);
-		writel(0x00000b51, &phy->mr0);
-	} else {
-		writel(0x999cbb66, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a878400, &phy->dtpr[1]);
-		else
-			writel(0x1a878400, &phy->dtpr[1]);
-		writel(0xa00214f8, &phy->dtpr[2]);
-		writel(0x00000d71, &phy->mr0);
-	}
-	writel(0x00000006, &phy->mr1);
-	if (freq == 1333)
-		writel(0x00000290, &phy->mr2);
-	else
-		writel(0x00000298, &phy->mr2);
-
-	writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
-
-	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
-		;
-
-	writel(0x0300C473, &phy->pgcr[1]);
-	writel(0x0000005D, &phy->zq[0].cr[1]);
-
-	return 0;
-}
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
index 206fabdd0b..a466118258 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h
@@ -172,10 +172,6 @@ struct ddrphy {
 #ifndef __ASSEMBLY__
 int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
 			bool ddr3plus);
-int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
-			 bool ddr3plus);
-int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
-			 bool ddr3plus);
 void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
 int ddrphy_training(struct ddrphy __iomem *phy);
 #endif
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
index 38dd338c85..877f5ef9cc 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
@@ -138,32 +138,32 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
-	ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size,
-			     bd->dram_ddr3plus);
+	ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size,
+			    bd->dram_ddr3plus);
 
 	ddrphy_prepare_training(phy0_0, 0);
 	ddrphy_training(phy0_0);
 
 	writel(0x00000103, dramcont0 + UMC_DIOCTLA);
 
-	ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size,
-			     bd->dram_ddr3plus);
+	ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size,
+			    bd->dram_ddr3plus);
 
 	ddrphy_prepare_training(phy0_1, 1);
 	ddrphy_training(phy0_1);
 
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
-	ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size,
-			     bd->dram_ddr3plus);
+	ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size,
+			    bd->dram_ddr3plus);
 
 	ddrphy_prepare_training(phy1_0, 0);
 	ddrphy_training(phy1_0);
 
 	writel(0x00000103, dramcont1 + UMC_DIOCTLA);
 
-	ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size,
-			     bd->dram_ddr3plus);
+	ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size,
+			    bd->dram_ddr3plus);
 
 	ddrphy_prepare_training(phy1_1, 1);
 	ddrphy_training(phy1_1);
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
index 3cbb7ba765..a27f91f895 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
@@ -97,14 +97,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
-	ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
+	ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
 
 	ddrphy_prepare_training(phy0_0, 0);
 	ddrphy_training(phy0_0);
 
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
-	ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
+	ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
 
 	ddrphy_prepare_training(phy1_0, 1);
 	ddrphy_training(phy1_0);