ppc4xx: remove G2000 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

9 files changed, 1 insertions, 1432 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 6c4759a768..e7163c1b4c 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -13,9 +13,6 @@ config TARGET_CSB272
 config TARGET_CSB472
 	bool "Support csb472"
 
-config TARGET_G2000
-	bool "Support G2000"
-
 config TARGET_JSE
 	bool "Support JSE"
 
@@ -218,7 +215,6 @@ source "board/esd/plu405/Kconfig"
 source "board/esd/pmc405de/Kconfig"
 source "board/esd/pmc440/Kconfig"
 source "board/esd/vom405/Kconfig"
-source "board/g2000/Kconfig"
 source "board/gdsys/405ep/Kconfig"
 source "board/gdsys/405ex/Kconfig"
 source "board/gdsys/dlvision/Kconfig"
diff --git a/board/g2000/Kconfig b/board/g2000/Kconfig
deleted file mode 100644
index 031fae991d..0000000000
--- a/board/g2000/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_G2000
-
-config SYS_BOARD
-	default "g2000"
-
-config SYS_CONFIG_NAME
-	default "G2000"
-
-endif
diff --git a/board/g2000/MAINTAINERS b/board/g2000/MAINTAINERS
deleted file mode 100644
index 8171b103b5..0000000000
--- a/board/g2000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-G2000 BOARD
-M:	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:	Maintained
-F:	board/g2000/
-F:	include/configs/G2000.h
-F:	configs/G2000_defconfig
diff --git a/board/g2000/Makefile b/board/g2000/Makefile
deleted file mode 100644
index 74c8053acc..0000000000
--- a/board/g2000/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= g2000.o strataflash.o
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
deleted file mode 100644
index a64f946ab4..0000000000
--- a/board/g2000/g2000.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-
-#define MEM_MCOPT1_INIT_VAL     0x00800000
-#define MEM_RTR_INIT_VAL        0x04070000
-#define MEM_PMIT_INIT_VAL       0x07c00000
-#define MEM_MB0CF_INIT_VAL      0x00082001
-#define MEM_MB1CF_INIT_VAL      0x04082000
-#define MEM_SDTR1_INIT_VAL      0x00854005
-#define SDRAM0_CFG_ENABLE       0x80000000
-
-#define CONFIG_SYS_SDRAM_SIZE          0x04000000      /* 64 MB */
-
-int board_early_init_f (void)
-{
-#if 0 /* test-only */
-	mtdcr (UIC0SR, 0xFFFFFFFF);      /* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);      /* disable all ints */
-	mtdcr (UIC0CR, 0x00000010);
-	mtdcr (UIC0PR, 0xFFFF7FF0);      /* set int polarities */
-	mtdcr (UIC0TR, 0x00000010);      /* set int trigger levels */
-	mtdcr (UIC0SR, 0xFFFFFFFF);      /* clear all ints */
-#else
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(UIC0PR, 0xFFFFFFF0);       /* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-#endif
-
-#if 1 /* test-only */
-	/*
-	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
-	 */
-	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-#endif
-
-	return 0;
-}
-
-
-int misc_init_f (void)
-{
-	return 0;  /* dummy implementation */
-}
-
-
-int misc_init_r (void)
-{
-#if defined(CONFIG_CMD_NAND)
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);
-#endif
-
-	return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof(str));
-
-	puts ("Board: ");
-
-	if (i == -1) {
-		puts ("### No HW ID - assuming G2000");
-	} else {
-		puts(str);
-	}
-
-	putc ('\n');
-
-	return 0;
-}
-
-
-/* -------------------------------------------------------------------------
-  G2000 rev B is an embeded design. we don't read for spd of this version.
-  Doing static SDRAM controller configuration in the following section.
-   ------------------------------------------------------------------------- */
-
-long int init_sdram_static_settings(void)
-{
-	/* disable memcontroller so updates work */
-	mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL);
-	mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL);
-	mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL);
-	mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL);
-	mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL);
-	mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL);
-
-	/* SDRAM have a power on delay,  500 micro should do */
-	udelay(500);
-	mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE);
-
-	return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
- }
-
-
-phys_size_t initdram (int board_type)
-{
-	long int ret;
-
-/* flzt, we can still turn this on in the future */
-/* #ifdef CONFIG_SPD_EEPROM
-	ret = spd_sdram ();
-#else
-	ret = init_sdram_static_settings();
-#endif
-*/
-
-	ret = init_sdram_static_settings();
-
-	return ret;
-}
-
-#if 0 /* test-only !!! */
-int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong ap, cr;
-
-	printf("\nEBC registers for PPC405GP:\n");
-	mfebc(PB0AP, ap); mfebc(PB0CR, cr);
-	printf("0: AP=%08lx CP=%08lx\n", ap, cr);
-	mfebc(PB1AP, ap); mfebc(PB1CR, cr);
-	printf("1: AP=%08lx CP=%08lx\n", ap, cr);
-	mfebc(PB2AP, ap); mfebc(PB2CR, cr);
-	printf("2: AP=%08lx CP=%08lx\n", ap, cr);
-	mfebc(PB3AP, ap); mfebc(PB3CR, cr);
-	printf("3: AP=%08lx CP=%08lx\n", ap, cr);
-	mfebc(PB4AP, ap); mfebc(PB4CR, cr);
-	printf("4: AP=%08lx CP=%08lx\n", ap, cr);
-	printf("\n");
-
-	return 0;
-}
-U_BOOT_CMD(
-	dumpebc,	1,	1,	do_dumpebc,
-	"Dump all EBC registers",
-	""
-);
-
-
-int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int i;
-
-	printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
-	for (i=0; i<=0x1e0; i++) {
-		if (!(i % 0x8)) {
-			printf("\n%04x ", i);
-		}
-		printf("%08lx ", get_dcr(i));
-	}
-	printf("\n");
-
-	return 0;
-}
-U_BOOT_CMD(
-	dumpdcr,	1,	1,	do_dumpdcr,
-	"Dump all DCR registers",
-	""
-);
-
-
-int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
-	printf("\n%04x %08x ", 947, mfspr(947));
-	printf("\n%04x %08x ", 9, mfspr(9));
-	printf("\n%04x %08x ", 1014, mfspr(1014));
-	printf("\n%04x %08x ", 1015, mfspr(1015));
-	printf("\n%04x %08x ", 1010, mfspr(1010));
-	printf("\n%04x %08x ", 957, mfspr(957));
-	printf("\n%04x %08x ", 1008, mfspr(1008));
-	printf("\n%04x %08x ", 1018, mfspr(1018));
-	printf("\n%04x %08x ", 954, mfspr(954));
-	printf("\n%04x %08x ", 950, mfspr(950));
-	printf("\n%04x %08x ", 951, mfspr(951));
-	printf("\n%04x %08x ", 981, mfspr(981));
-	printf("\n%04x %08x ", 980, mfspr(980));
-	printf("\n%04x %08x ", 982, mfspr(982));
-	printf("\n%04x %08x ", 1012, mfspr(1012));
-	printf("\n%04x %08x ", 1013, mfspr(1013));
-	printf("\n%04x %08x ", 948, mfspr(948));
-	printf("\n%04x %08x ", 949, mfspr(949));
-	printf("\n%04x %08x ", 1019, mfspr(1019));
-	printf("\n%04x %08x ", 979, mfspr(979));
-	printf("\n%04x %08x ", 8, mfspr(8));
-	printf("\n%04x %08x ", 945, mfspr(945));
-	printf("\n%04x %08x ", 987, mfspr(987));
-	printf("\n%04x %08x ", 287, mfspr(287));
-	printf("\n%04x %08x ", 953, mfspr(953));
-	printf("\n%04x %08x ", 955, mfspr(955));
-	printf("\n%04x %08x ", 272, mfspr(272));
-	printf("\n%04x %08x ", 273, mfspr(273));
-	printf("\n%04x %08x ", 274, mfspr(274));
-	printf("\n%04x %08x ", 275, mfspr(275));
-	printf("\n%04x %08x ", 260, mfspr(260));
-	printf("\n%04x %08x ", 276, mfspr(276));
-	printf("\n%04x %08x ", 261, mfspr(261));
-	printf("\n%04x %08x ", 277, mfspr(277));
-	printf("\n%04x %08x ", 262, mfspr(262));
-	printf("\n%04x %08x ", 278, mfspr(278));
-	printf("\n%04x %08x ", 263, mfspr(263));
-	printf("\n%04x %08x ", 279, mfspr(279));
-	printf("\n%04x %08x ", 26, mfspr(26));
-	printf("\n%04x %08x ", 27, mfspr(27));
-	printf("\n%04x %08x ", 990, mfspr(990));
-	printf("\n%04x %08x ", 991, mfspr(991));
-	printf("\n%04x %08x ", 956, mfspr(956));
-	printf("\n%04x %08x ", 284, mfspr(284));
-	printf("\n%04x %08x ", 285, mfspr(285));
-	printf("\n%04x %08x ", 986, mfspr(986));
-	printf("\n%04x %08x ", 984, mfspr(984));
-	printf("\n%04x %08x ", 256, mfspr(256));
-	printf("\n%04x %08x ", 1, mfspr(1));
-	printf("\n%04x %08x ", 944, mfspr(944));
-	printf("\n");
-
-	return 0;
-}
-U_BOOT_CMD(
-	dumpspr,	1,	1,	do_dumpspr,
-	"Dump all SPR registers",
-	""
-);
-#endif
diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c
deleted file mode 100644
index 1d29eb4325..0000000000
--- a/board/g2000/strataflash.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-#undef  DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for ppcboot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI			0x98
-#define FLASH_CMD_READ_ID		0x90
-#define FLASH_CMD_RESET			0xff
-#define FLASH_CMD_BLOCK_ERASE		0x20
-#define FLASH_CMD_ERASE_CONFIRM		0xD0
-#define FLASH_CMD_WRITE			0x40
-#define FLASH_CMD_PROTECT		0x60
-#define FLASH_CMD_PROTECT_SET		0x01
-#define FLASH_CMD_PROTECT_CLEAR		0xD0
-#define FLASH_CMD_CLEAR_STATUS		0x50
-#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
-
-#define FLASH_STATUS_DONE		0x80
-#define FLASH_STATUS_ESS		0x40
-#define FLASH_STATUS_ECLBS		0x20
-#define FLASH_STATUS_PSLBS		0x10
-#define FLASH_STATUS_VPENS		0x08
-#define FLASH_STATUS_PSS		0x04
-#define FLASH_STATUS_DPS		0x02
-#define FLASH_STATUS_R			0x01
-#define FLASH_STATUS_PROTECT		0x01
-
-#define FLASH_OFFSET_CFI		0x55
-#define FLASH_OFFSET_CFI_RESP		0x10
-#define FLASH_OFFSET_WTOUT		0x1F
-#define FLASH_OFFSET_WBTOUT             0x20
-#define FLASH_OFFSET_ETOUT		0x21
-#define FLASH_OFFSET_CETOUT             0x22
-#define FLASH_OFFSET_WMAX_TOUT		0x23
-#define FLASH_OFFSET_WBMAX_TOUT         0x24
-#define FLASH_OFFSET_EMAX_TOUT		0x25
-#define FLASH_OFFSET_CEMAX_TOUT         0x26
-#define FLASH_OFFSET_SIZE		0x27
-#define FLASH_OFFSET_INTERFACE          0x28
-#define FLASH_OFFSET_BUFFER_SIZE        0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
-#define FLASH_OFFSET_ERASE_REGIONS	0x2D
-#define FLASH_OFFSET_PROTECT		0x02
-#define FLASH_OFFSET_USER_PROTECTION    0x85
-#define FLASH_OFFSET_INTEL_PROTECTION   0x81
-
-#define FLASH_MAN_CFI			0x01000000
-
-typedef union {
-	unsigned char c;
-	unsigned short w;
-	unsigned long l;
-} cfiword_t;
-
-typedef union {
-	unsigned char * cp;
-	unsigned short *wp;
-	unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
-{
-	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
-}
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
-	uchar *cp;
-	cp = flash_make_addr(info, 0, offset);
-	return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
-{
-    uchar * addr;
-
-    addr = flash_make_addr(info, sect, offset);
-    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
-{
-    uchar * addr;
-
-    addr = flash_make_addr(info, sect, offset);
-    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
-	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-	unsigned long size;
-	int i;
-	unsigned long  address;
-
-
-	/* The flash is positioned back to back, with the demultiplexing of the chip
-	 * based on the A24 address line.
-	 *
-	 */
-
-	address = CONFIG_SYS_FLASH_BASE;
-	size = 0;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		size += flash_info[i].size = flash_get_size(address, i);
-		address += CONFIG_SYS_FLASH_INCREMENT;
-		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
-				flash_info[0].size, flash_info[i].size<<20);
-		}
-	}
-
-#if 0 /* test-only */
-	/* Monitor protection ON by default */
-#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
-	for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
-		(void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#else
-	/* monitor protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       - CONFIG_SYS_MONITOR_LEN,
-		       - 1, &flash_info[1]);
-#endif
-
-	return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	int rcode = 0;
-	int prot;
-	int sect;
-
-	if( info->flash_id != FLASH_MAN_CFI) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-	if ((s_first < 0) || (s_first > s_last)) {
-		printf ("- no sectors to erase\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) { /* not protected */
-			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
-			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
-			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
-			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
-				rcode = 1;
-			} else
-				printf(".");
-		}
-	}
-	printf (" done\n");
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id != FLASH_MAN_CFI) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	printf("CFI conformant FLASH (%d x %d)",
-	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
-	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
-		int k;
-		int size;
-		int erased;
-		volatile unsigned long *flash;
-
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count-1))
-		  size = info->start[i+1] - info->start[i];
-		else
-		  size = info->start[0] + info->size - info->start[i];
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;        /* divide by 4 for longword access */
-		for (k=0; k<size; k++)
-		  {
-		    if (*flash++ != 0xffffffff)
-		      {
-			erased = 0;
-			break;
-		      }
-		  }
-
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		/* print empty and read-only info */
-		printf (" %08lX%s%s",
-			info->start[i],
-			erased ? " E" : "  ",
-			info->protect[i] ? "RO " : "   ");
-#else
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-#endif
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong wp;
-	ulong cp;
-	int aln;
-	cfiword_t cword;
-	int i, rc;
-
-	/* get lower aligned address */
-	wp = (addr & ~(info->portwidth - 1));
-
-	/* handle unaligned start */
-	if((aln = addr - wp) != 0) {
-		cword.l = 0;
-		cp = wp;
-		for(i=0;i<aln; ++i, ++cp)
-			flash_add_byte(info, &cword, (*(uchar *)cp));
-
-		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
-			flash_add_byte(info, &cword, *src++);
-			cnt--;
-			cp++;
-		}
-		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
-			flash_add_byte(info, &cword, (*(uchar *)cp));
-		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
-			return rc;
-		wp = cp;
-	}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-	while(cnt >= info->portwidth) {
-		i = info->buffer_size > cnt? cnt: info->buffer_size;
-		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
-			return rc;
-		wp += i;
-		src += i;
-		cnt -=i;
-	}
-#else
-	/* handle the aligned part */
-	while(cnt >= info->portwidth) {
-		cword.l = 0;
-		for(i = 0; i < info->portwidth; i++) {
-			flash_add_byte(info, &cword, *src++);
-		}
-		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
-			return rc;
-		wp += info->portwidth;
-		cnt -= info->portwidth;
-	}
-#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	cword.l = 0;
-	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
-		flash_add_byte(info, &cword, *src++);
-		--cnt;
-	}
-	for (; i<info->portwidth; ++i, ++cp) {
-		flash_add_byte(info, & cword, (*(uchar *)cp));
-	}
-
-	return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
-	int retcode = 0;
-
-	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
-	if(prot)
-		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
-	else
-		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
-	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
-					 prot?"protect":"unprotect")) == 0) {
-
-		info->protect[sector] = prot;
-		/* Intel's unprotect unprotects all locking */
-		if(prot == 0) {
-			int i;
-			for(i = 0 ; i<info->sector_count; i++) {
-				if(info->protect[i])
-					flash_real_protect(info, i, 1);
-			}
-		}
-	}
-
-	return retcode;
-}
-/*-----------------------------------------------------------------------
- *  wait for XSR.7 to be set. Time out with an error if it does not.
- *  This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
-	ulong start;
-
-	/* Wait for command completion */
-	start = get_timer (0);
-	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
-		if (get_timer(start) > info->erase_blk_tout) {
-			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
-			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
-			return ERR_TIMOUT;
-		}
-	}
-	return ERR_OK;
-}
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
-	int retcode;
-	retcode = flash_status_check(info, sector, tout, prompt);
-	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
-		retcode = ERR_INVAL;
-		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
-		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
-			printf("Command Sequence Error.\n");
-		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
-			printf("Block Erase Error.\n");
-			retcode = ERR_NOT_ERASED;
-		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
-			printf("Locking Error\n");
-		}
-		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
-			printf("Block locked.\n");
-			retcode = ERR_PROTECTED;
-		}
-		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
-			printf("Vpp Low Error.\n");
-	}
-	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
-	return retcode;
-}
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
-{
-	switch(info->portwidth) {
-	case FLASH_CFI_8BIT:
-		cword->c = c;
-		break;
-	case FLASH_CFI_16BIT:
-		cword->w = (cword->w << 8) | c;
-		break;
-	case FLASH_CFI_32BIT:
-		cword->l = (cword->l << 8) | c;
-	}
-}
-
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
-{
-	int i;
-	uchar *cp = (uchar *)cmdbuf;
-	for(i=0; i< info->portwidth; i++)
-		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-
-	volatile cfiptr_t addr;
-	cfiword_t cword;
-	addr.cp = flash_make_addr(info, sect, offset);
-	flash_make_cmd(info, cmd, &cword);
-	switch(info->portwidth) {
-	case FLASH_CFI_8BIT:
-		*addr.cp = cword.c;
-		break;
-	case FLASH_CFI_16BIT:
-		*addr.wp = cword.w;
-		break;
-	case FLASH_CFI_32BIT:
-		*addr.lp = cword.l;
-		break;
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-	cfiptr_t cptr;
-	cfiword_t cword;
-	int retval;
-	cptr.cp = flash_make_addr(info, sect, offset);
-	flash_make_cmd(info, cmd, &cword);
-	switch(info->portwidth) {
-	case FLASH_CFI_8BIT:
-		retval = (cptr.cp[0] == cword.c);
-		break;
-	case FLASH_CFI_16BIT:
-		retval = (cptr.wp[0] == cword.w);
-		break;
-	case FLASH_CFI_32BIT:
-		retval = (cptr.lp[0] == cword.l);
-		break;
-	default:
-		retval = 0;
-		break;
-	}
-	return retval;
-}
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-	cfiptr_t cptr;
-	cfiword_t cword;
-	int retval;
-	cptr.cp = flash_make_addr(info, sect, offset);
-	flash_make_cmd(info, cmd, &cword);
-	switch(info->portwidth) {
-	case FLASH_CFI_8BIT:
-		retval = ((cptr.cp[0] & cword.c) == cword.c);
-		break;
-	case FLASH_CFI_16BIT:
-		retval = ((cptr.wp[0] & cword.w) == cword.w);
-		break;
-	case FLASH_CFI_32BIT:
-		retval = ((cptr.lp[0] & cword.l) == cword.l);
-		break;
-	default:
-		retval = 0;
-		break;
-	}
-	return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
-*/
-static int flash_detect_cfi(flash_info_t * info)
-{
-
-	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
-	    info->portwidth <<= 1) {
-		for(info->chipwidth =FLASH_CFI_BY8;
-		    info->chipwidth <= info->portwidth;
-		    info->chipwidth <<= 1) {
-			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
-			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
-			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
-			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
-				return 1;
-		}
-	}
-	return 0;
-}
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size (ulong base, int banknum)
-{
-	flash_info_t * info = &flash_info[banknum];
-	int i, j;
-	int sect_cnt;
-	unsigned long sector;
-	unsigned long tmp;
-	int size_ratio;
-	uchar num_erase_regions;
-	int  erase_region_size;
-	int  erase_region_count;
-
-	info->start[0] = base;
-
-	if(flash_detect_cfi(info)){
-#ifdef DEBUG_FLASH
-		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
-		size_ratio = info->portwidth / info->chipwidth;
-		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-#ifdef DEBUG_FLASH
-		printf("found %d erase regions\n", num_erase_regions);
-#endif
-		sect_cnt = 0;
-		sector = base;
-		for(i = 0 ; i < num_erase_regions; i++) {
-			if(i > NUM_ERASE_REGIONS) {
-				printf("%d erase regions found, only %d used\n",
-				       num_erase_regions, NUM_ERASE_REGIONS);
-				break;
-			}
-			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
-			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
-			tmp >>= 16;
-			erase_region_count = (tmp & 0xffff) +1;
-			for(j = 0; j< erase_region_count; j++) {
-				info->start[sect_cnt] = sector;
-				sector += (erase_region_size * size_ratio);
-				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
-				sect_cnt++;
-			}
-		}
-
-		info->sector_count = sect_cnt;
-		/* multiply the size by the number of chips */
-		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
-		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
-		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
-		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
-		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
-		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
-		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
-		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
-		info->flash_id = FLASH_MAN_CFI;
-	}
-
-	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-	return(info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
-{
-
-	cfiptr_t cptr;
-	int flag;
-
-	cptr.cp = (uchar *)dest;
-
-	/* Check if Flash is (sufficiently) erased */
-	switch(info->portwidth) {
-	case FLASH_CFI_8BIT:
-		flag = ((cptr.cp[0] & cword.c) == cword.c);
-		break;
-	case FLASH_CFI_16BIT:
-		flag = ((cptr.wp[0] & cword.w) == cword.w);
-		break;
-	case FLASH_CFI_32BIT:
-		flag = ((cptr.lp[0] & cword.l)	== cword.l);
-		break;
-	default:
-		return 2;
-	}
-	if(!flag)
-		return 2;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
-	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
-	switch(info->portwidth) {
-	case FLASH_CFI_8BIT:
-		cptr.cp[0] = cword.c;
-		break;
-	case FLASH_CFI_16BIT:
-		cptr.wp[0] = cword.w;
-		break;
-	case FLASH_CFI_32BIT:
-		cptr.lp[0] = cword.l;
-		break;
-	}
-
-	/* re-enable interrupts if necessary */
-	if(flag)
-		enable_interrupts();
-
-	return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t *info, ulong addr)
-{
-	int sector;
-	for(sector = info->sector_count - 1; sector >= 0; sector--) {
-		if(addr >= info->start[sector])
-			break;
-	}
-	return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
-{
-
-	int sector;
-	int cnt;
-	int retcode;
-	volatile cfiptr_t src;
-	volatile cfiptr_t dst;
-
-	src.cp = cp;
-	dst.cp = (uchar *)dest;
-	sector = find_sector(info, dest);
-	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
-	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
-					 "write to buffer")) == ERR_OK) {
-		switch(info->portwidth) {
-		case FLASH_CFI_8BIT:
-			cnt = len;
-			break;
-		case FLASH_CFI_16BIT:
-			cnt = len >> 1;
-			if (len & 0x1) { /* test-only: unaligned size */
-				puts("\nUnalgined size!!!\n"); /* test-only */
-				cnt++;
-			}
-			break;
-		case FLASH_CFI_32BIT:
-			cnt = len >> 2;
-			break;
-		default:
-			return ERR_INVAL;
-			break;
-		}
-		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
-		while(cnt-- > 0) {
-			switch(info->portwidth) {
-			case FLASH_CFI_8BIT:
-				*dst.cp++ = *src.cp++;
-				break;
-			case FLASH_CFI_16BIT:
-				*dst.wp++ = *src.wp++;
-				break;
-			case FLASH_CFI_32BIT:
-				*dst.lp++ = *src.lp++;
-				break;
-			default:
-				return ERR_INVAL;
-				break;
-			}
-		}
-		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
-		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
-					     "buffer write");
-	}
-	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
-	return retcode;
-}
-#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/configs/G2000_defconfig b/configs/G2000_defconfig
deleted file mode 100644
index a01bc0f86b..0000000000
--- a/configs/G2000_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_G2000=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index a385bde485..69daaab394 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+G2000            ppc4xx      405ep          -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
 WUH405           ppc4xx      405ep          -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
 VOH405           ppc4xx      405ep          -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
 PMC405           ppc4xx      405gp          -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
deleted file mode 100644
index 0c66092e0b..0000000000
--- a/include/configs/G2000.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_G2000		1	/* ...on a PLU405 board		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
-
-#if 0 /* test-only */
-#define CONFIG_BAUDRATE		115200
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-#define CONFIG_PREBOOT
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off\0"				\
-	"addmisc=setenv bootargs ${bootargs} "				\
-		"console=ttyS0,${baudrate} "				\
-		"panic=1\0"						\
-	"flash_nfs=run nfsargs addip addmisc;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addmisc;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};"				\
-		"run nfsargs addip addmisc;bootm\0"			\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/g2000/pImage\0"				\
-	"kernel_addr=ff800000\0"				        \
-	"ramdisk_addr=ff900000\0"				        \
-	"pciconfighost=yes\0"				                \
-	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
-
-#if 0 /* test-only */
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#if 0 /* test-only */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*----------------------------------------------------------------------------*/
-/* adding Ethernet setting:  FTS OUI 00:11:0B */
-/*----------------------------------------------------------------------------*/
-#define CONFIG_ETHADDR          00:11:0B:00:00:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR         00:11:0B:00:00:02
-#define CONFIG_IPADDR		10.48.8.178
-#define CONFIG_IP1ADDR		10.48.8.188
-#define CONFIG_NETMASK		255.255.255.128
-#define CONFIG_SERVERIP		10.48.8.138
-
-/*-----------------------------------------------------------------------
- * RTC stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-
-#if 0 /* test-only */
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-
-#define CONFIG_SYS_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
-
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if 0 /* APC405 */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* test-only...*/
-#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* test-only */
-#else /* G2000 */
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_BASE		0xFF800000 /* test-only...*/
-#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* test-only */
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#if 1 /* test-only */
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
-				   /* total size of a CAT24WC16 is 2048 bytes */
-
-#else	/* DEFAULT: environment in flash, using redundand flash sectors */
-
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define CONFIG_ENV_ADDR		0xFFFA0000 /* environment starts before u-boot */
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128k bytes may be used for env vars*/
-
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
-/* CAT24WC08/16... */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Intel Strata Flash) initialization                            */
-#define CONFIG_SYS_EBC_PB0AP   0x92015480
-#define CONFIG_SYS_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 1 ( Power TAU) initialization               */
-/* #define CONFIG_SYS_EBC_PB1AP           0x04041000 */
-/* #define CONFIG_SYS_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
-#define CONFIG_SYS_EBC_PB1AP           0x00000000
-#define CONFIG_SYS_EBC_PB1CR           0x00000000
-
-/* Memory Bank 2 (Intel Flash) initialization                 */
-#define CONFIG_SYS_EBC_PB2AP           0x00000000
-#define CONFIG_SYS_EBC_PB2CR           0x00000000
-
-/* Memory Bank 3 (NAND) initialization                        */
-#define CONFIG_SYS_EBC_PB3AP           0x92015480
-#define CONFIG_SYS_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
-
-/* Memory Bank 4 (FPGA regs) initialization                                     */
-#define CONFIG_SYS_EBC_PB4AP           0x00000000
-#define CONFIG_SYS_EBC_PB4CR           0x00000000  /* leave it blank  */
-
-#define CONFIG_SYS_NAND_BASE   0xF4000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]     - External Bus Controller BLAST output
- * GPIO0[1-9]   - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- *
- * following GPIO setting changed for G20000, 080304
- */
-#define CONFIG_SYS_GPIO0_OSRL          0x40005555
-#define CONFIG_SYS_GPIO0_OSRH          0x40000110
-#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H         0x15555445
-#define CONFIG_SYS_GPIO0_TSRL          0x00000000
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000
-#define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 1
-#define PLLMR0_DEFAULT	 PLLMR0_266_66_33_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_66_33_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
-
-#endif	/* __CONFIG_H */