diff options
| author | Matthias Ludwig <mludwig@ultratronik.de> | 2009-06-20 11:01:50 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-07-06 21:52:12 +0200 |
| commit | 9c8c706c92e53433a871a563946c38075d76504d (patch) | |
| tree | 4dbbfb1754c8c1b55e4f4946557022dd65bd10fd | |
| parent | 0aafde1dc76d6d65d6be10bf499ec86d9ffee8b9 (diff) | |
| download | talos-obmc-uboot-9c8c706c92e53433a871a563946c38075d76504d.tar.gz talos-obmc-uboot-9c8c706c92e53433a871a563946c38075d76504d.zip | |
OMAP3EVM: fix typo. replace CS6 by CS5, no functionality change
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
| -rw-r--r-- | board/omap3/evm/evm.c | 16 | ||||
| -rw-r--r-- | include/asm-arm/arch-omap3/cpu.h | 5 |
2 files changed, 11 insertions, 10 deletions
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index c008c2e4aa..5fd5efad9c 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -92,17 +92,17 @@ void set_muxconf_regs(void) static void setup_net_chip(void) { gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; - gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE; + gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE; ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; /* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1); - writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2); - writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3); - writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4); - writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5); - writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6); - writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7); + writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1); + writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2); + writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3); + writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4); + writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5); + writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6); + writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index c544e0c5d3..a4ce45ab2c 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -84,9 +84,10 @@ typedef struct ctrl_id { /* GPMC CS3/cs4/cs6 not avaliable */ #define GPMC_BASE (OMAP34XX_GPMC_BASE) #define GPMC_CONFIG_CS0 0x60 -#define GPMC_CONFIG_CS6 0x150 +#define GPMC_CONFIG_CS5 0x150 + #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) -#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6) +#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5) #define GPMC_CONFIG_WP 0x10 #define GPMC_CONFIG_WIDTH 0x30 |
