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| author | Wolfgang Denk <wd@denx.de> | 2009-03-15 22:12:10 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-03-15 22:12:10 +0100 |
| commit | 45f93d4e3c0d2a083131d1c579908bfeb3011bb1 (patch) | |
| tree | 0b4ba3ece8e71c832af4fcdbd500f5a007fea5ea | |
| parent | 06ecf088478aed889a4153978c2e30fb02cf41ea (diff) | |
| parent | 394d30dd1ee23b80fd5e59e17ebe0feca927ab31 (diff) | |
| download | talos-obmc-uboot-45f93d4e3c0d2a083131d1c579908bfeb3011bb1.tar.gz talos-obmc-uboot-45f93d4e3c0d2a083131d1c579908bfeb3011bb1.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
| -rw-r--r-- | cpu/mpc83xx/cpu_init.c | 2 | ||||
| -rw-r--r-- | cpu/mpc83xx/spd_sdram.c | 16 |
2 files changed, 11 insertions, 7 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 491c2e5c3b..8e9c875599 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -106,7 +106,7 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | - (CONFIG_SYS_SCCR_ENCCM << SCCR_PCICM_SHIFT); + (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT); #endif #ifdef CONFIG_SYS_SCCR_PCICM diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index ff15cda7a8..4704d2006f 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -219,7 +219,8 @@ long int spd_sdram() ddr->cs_config[0] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); @@ -231,8 +232,9 @@ long int spd_sdram() ddr->cs_config[1] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); } @@ -242,7 +244,8 @@ long int spd_sdram() ddr->cs_config[2] = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) | (spd.ncol_addr - 8) ); debug("\n"); debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); @@ -254,8 +257,9 @@ long int spd_sdram() ddr->cs_config[3] = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); + | ((spd.nbanks == 8 ? 1 : 0) << 14) + | ((spd.nrow_addr - 12) << 8) + | (spd.ncol_addr - 8) ); debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); } |
