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| author | Vladimir Zapolskiy <vz@mleia.com> | 2015-07-06 07:22:10 +0300 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2015-08-11 13:42:34 -0500 |
| commit | 23f5db0e26f0e6c25ba143e700b4812efdd5f941 (patch) | |
| tree | a8e7accdf656acedafba26ab7c09316106bf607d | |
| parent | fe0596cac3079a74eeee93e2940010a7a158c58d (diff) | |
| download | talos-obmc-uboot-23f5db0e26f0e6c25ba143e700b4812efdd5f941.tar.gz talos-obmc-uboot-23f5db0e26f0e6c25ba143e700b4812efdd5f941.zip | |
net: lpc32xx: improve MAC configuration on reset and initialization
This change rearranges general MAC configuration and PHY specific
configuration of MAC registers (duplex mode and speed), before this
change set bits related to PHY configuration in MAC2 and COMMAND
registers are rewritten by the following writing to the registers.
Without the change auto negotiation on boot quite often is not
completed in reasonable time:
Waiting for PHY auto negotiation to complete......... TIMEOUT !
Additionally MAC1_SOFT_RESET clear bit is removed since it is done in
preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead
added missing MCFG_RESET_MII_MGMT on device initialization.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
| -rw-r--r-- | drivers/net/lpc32xx_eth.c | 33 |
1 files changed, 15 insertions, 18 deletions
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c index 6033392945..f883a254c4 100644 --- a/drivers/net/lpc32xx_eth.c +++ b/drivers/net/lpc32xx_eth.c @@ -151,7 +151,7 @@ struct lpc32xx_eth_registers { #define SUPP_SPEED 0x00000100 /* MCFG register bitfields/masks and offsets (see Table 292) */ -#define MCFG_CLOCK_SELECT_MASK 0x0000001C +#define MCFG_RESET_MII_MGMT 0x00008000 /* divide clock by 28 (see Table 293) */ #define MCFG_CLOCK_SELECT_DIV28 0x0000001C @@ -459,8 +459,19 @@ static int lpc32xx_eth_init(struct eth_device *dev) struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; int index; - /* Release SOFT reset to let MII talk to PHY */ - clrbits_le32(®s->mac1, MAC1_SOFT_RESET); + /* Initial MAC initialization */ + writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1); + writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2); + writel(PKTSIZE_ALIGN, ®s->maxf); + + /* Retries: 15 (0xF). Collision window: 57 (0x37). */ + writel(0x370F, ®s->clrt); + + /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ + writel(0x0012, ®s->ipgr); + + /* pass runt (smaller than 64 bytes) frames */ + writel(COMMAND_PASSRUNTFRAME, ®s->command); /* Configure Full/Half Duplex mode */ if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) { @@ -477,20 +488,6 @@ static int lpc32xx_eth_init(struct eth_device *dev) else writel(0, ®s->supp); - /* Initial MAC initialization */ - writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1); - writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2); - writel(PKTSIZE_ALIGN, ®s->maxf); - - /* Retries: 15 (0xF). Collision window: 57 (0x37). */ - writel(0x370F, ®s->clrt); - - /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ - writel(0x0012, ®s->ipgr); - - /* pass runt (smaller than 64 bytes) frames */ - writel(COMMAND_PASSRUNTFRAME, ®s->command); - /* Save station address */ writel((unsigned long) (dev->enetaddr[0] | (dev->enetaddr[1] << 8)), ®s->sa2); @@ -604,7 +601,7 @@ int lpc32xx_eth_initialize(bd_t *bis) * Set RMII management clock rate. With HCLK at 104 MHz and * a divider of 28, this will be 3.72 MHz. */ - + writel(MCFG_RESET_MII_MGMT, ®s->mcfg); writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg); /* Reset all MAC logic */ |
