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| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-11-21 13:38:55 -0800 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-02-19 09:41:22 +0100 |
| commit | 19605e2e038eb7266c74c4aba6a4d6c9f33db797 (patch) | |
| tree | feccba34ab52470a9d3676f538b506564e49ff09 | |
| parent | 97598fcf10eba577622f3387eaecd43dd710da0d (diff) | |
| download | talos-obmc-uboot-19605e2e038eb7266c74c4aba6a4d6c9f33db797.tar.gz talos-obmc-uboot-19605e2e038eb7266c74c4aba6a4d6c9f33db797.zip | |
serial_zynq: Migrate to Zynq clock framework
Remove hard coded frequencies and use Zynq's clock framework to obtain
the UART clock frequency.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | drivers/serial/serial_zynq.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 9a1ee00e9c..22c6bf099c 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <linux/compiler.h> #include <serial.h> +#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ @@ -45,23 +46,13 @@ static struct uart_zynq *uart_zynq_ports[2] = { # define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE #endif -#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK0) -# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 -#endif -#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK1) -# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 -#endif - struct uart_zynq_params { u32 baudrate; - u32 clock; }; static struct uart_zynq_params uart_zynq_ports_param[2] = { [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, - [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, - [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, }; /* Set up the baud rate in gd struct */ @@ -71,7 +62,7 @@ static void uart_zynq_serial_setbrg(const int port) unsigned int calc_bauderror, bdiv, bgen; unsigned long calc_baud = 0; unsigned long baud = uart_zynq_ports_param[port].baudrate; - unsigned long clock = uart_zynq_ports_param[port].clock; + unsigned long clock = get_uart_clk(port); struct uart_zynq *regs = uart_zynq_ports[port]; /* master clock |
