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| author | Jeffrey Mann <mannj@embeddedplanet.com> | 2007-05-07 19:42:49 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-05-07 19:42:49 +0200 |
| commit | 193b4a3bb3acaddf798da8de0da05d94ba8774ee (patch) | |
| tree | 71474dd04f5d91e908d326981f16d2dd341a5c00 | |
| parent | ac4cd59d59c9bf3f89cb7a344abf8184d678f562 (diff) | |
| download | talos-obmc-uboot-193b4a3bb3acaddf798da8de0da05d94ba8774ee.tar.gz talos-obmc-uboot-193b4a3bb3acaddf798da8de0da05d94ba8774ee.zip | |
[PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config file
A '3' got cut off in the formatting of the last patch to automatically
change the clock speed of the system clock on sequoia board.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | include/configs/sequoia.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index b7f79c26eb..e1572ba39c 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -40,7 +40,7 @@ #define CONFIG_4xx 1 /* ... PPC4xx family */ /* Detect Sequoia PLL input clock automatically via CPLD bit */ #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ - 3333333 : 33000000) + 33333333 : 33000000) #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
