From d4f4c0aa8e36f69e46360b3d3569dc15d6099894 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?H=C3=A5vard=20Skinnemoen?= Date: Fri, 6 Jun 2008 18:04:52 +0200 Subject: [MTD] [NAND] rename at91_nand -> atmel_nand: file names and Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AT91 NAND driver needs just a few tiny modifications to work on AVR32 as well. Rename it atmel_nand to reflect this. Also move the ECC register definitions into drivers/mtd/nand since they are only useful to the atmel_nand driver, and get rid of the useless filename at the top of each file. Signed-off-by: Håvard Skinnemoen Signed-off-by: David Woodhouse --- include/asm-arm/arch-at91/at91_ecc.h | 38 ------------------------------------ 1 file changed, 38 deletions(-) delete mode 100644 include/asm-arm/arch-at91/at91_ecc.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h deleted file mode 100644 index 1e5a8caca2d1..000000000000 --- a/include/asm-arm/arch-at91/at91_ecc.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * include/asm-arm/arch-at91/at91_ecc.h - * - * Error Corrected Code Controller (ECC) - System peripherals regsters. - * Based on AT91SAM9260 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef AT91_ECC_H -#define AT91_ECC_H - -#define AT91_ECC_CR 0x00 /* Control register */ -#define AT91_ECC_RST (1 << 0) /* Reset parity */ - -#define AT91_ECC_MR 0x04 /* Mode register */ -#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ -#define AT91_ECC_PAGESIZE_528 (0) -#define AT91_ECC_PAGESIZE_1056 (1) -#define AT91_ECC_PAGESIZE_2112 (2) -#define AT91_ECC_PAGESIZE_4224 (3) - -#define AT91_ECC_SR 0x08 /* Status register */ -#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ -#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ -#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ - -#define AT91_ECC_PR 0x0c /* Parity register */ -#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ -#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ - -#define AT91_ECC_NPR 0x10 /* NParity register */ -#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ - -#endif -- cgit v1.2.1 From 3c3796cc32b6e53653a5eb868dc959b8c2779db9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?H=C3=A5vard=20Skinnemoen?= Date: Fri, 6 Jun 2008 18:04:53 +0200 Subject: [MTD] [NAND] rename at91_nand -> atmel_nand: internal symbols MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is basically s/at91_nand/atmel_nand/g with some manual inspection. Signed-off-by: Håvard Skinnemoen Signed-off-by: David Woodhouse --- include/asm-arm/arch-at91/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h index dc189f01c5b3..6296922a6843 100644 --- a/include/asm-arm/arch-at91/board.h +++ b/include/asm-arm/arch-at91/board.h @@ -85,7 +85,7 @@ struct at91_usbh_data { extern void __init at91_add_device_usbh(struct at91_usbh_data *data); /* NAND / SmartMedia */ -struct at91_nand_data { +struct atmel_nand_data { u8 enable_pin; /* chip enable */ u8 det_pin; /* card detect */ u8 rdy_pin; /* ready/busy */ @@ -94,7 +94,7 @@ struct at91_nand_data { u8 bus_width_16; /* buswidth is 16 bit */ struct mtd_partition* (*partition_info)(int, int*); }; -extern void __init at91_add_device_nand(struct at91_nand_data *data); +extern void __init at91_add_device_nand(struct atmel_nand_data *data); /* I2C*/ extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); -- cgit v1.2.1 From 75f10b465af9efd59906e9079ed9cbda7e0f7a43 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 22 May 2008 16:20:18 +0100 Subject: [ARM] 5047/2: Support resetting by asserting GPIO pin This adds support for resetting via assertion of GPIO pin. This e.g. is used on Sharp Zaurus SL-6000. Signed-off-by: Dmitry Baryshkov Acked-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/hardware.h | 5 +++++ include/asm-arm/arch-pxa/system.h | 17 +---------------- 2 files changed, 6 insertions(+), 16 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index e25558faa5a4..5547ec797ad0 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -205,6 +205,11 @@ static inline void __deprecated pxa_set_cken(int clock, int enable) */ extern unsigned int get_memclk_frequency_10khz(void); +/* + * register GPIO as reset generator + */ +extern int init_gpio_reset(int gpio); + #endif #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h index 9aa6c2e939e8..14894ae3fa67 100644 --- a/include/asm-arm/arch-pxa/system.h +++ b/include/asm-arm/arch-pxa/system.h @@ -20,19 +20,4 @@ static inline void arch_idle(void) } -static inline void arch_reset(char mode) -{ - if (cpu_is_pxa2xx()) - RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; - - if (mode == 's') { - /* Jump into ROM at address 0 */ - cpu_reset(0); - } else { - /* Initialize the watchdog and let it fire */ - OWER = OWER_WME; - OSSR = OSSR_M3; - OSMR3 = OSCR + 368640; /* ... in 100 ms */ - } -} - +void arch_reset(char mode); -- cgit v1.2.1 From b032fccca80cbbedaa80e5a72a202a43f08aa97e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 12 Jun 2008 11:42:07 +0100 Subject: [ARM] 5083/2: Tosa: fix IrDA transciver powerup. On tosa the tranciver LED isn't powered down if the GPIO47 (STUART_TX) isn't configured as low-level. Power it down if IrDA is off to save a bit of power. Signed-off-by: Dmitry Baryshkov Signed-off-by: Russell King --- include/asm-arm/arch-pxa/tosa.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h index c5b6fde6907c..188226216154 100644 --- a/include/asm-arm/arch-pxa/tosa.h +++ b/include/asm-arm/arch-pxa/tosa.h @@ -99,6 +99,7 @@ #define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ #define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ #define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ +#define TOSA_GPIO_IRDA_TX (47) #define TOSA_GPIO_TG_SPI_SCLK (81) #define TOSA_GPIO_TG_SPI_CS (82) #define TOSA_GPIO_TG_SPI_MOSI (83) -- cgit v1.2.1 From bf0116e54e185fd63025f2b975f0f1616ffe41f1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 14 Jun 2008 11:42:02 +0100 Subject: [ARM] 5097/1: Tosa: support TC6393XB device Add definitions for Toshiba TC6393XB companion chip and register the tc6393xb device. Signed-off-by: Dmitry Baryshkov Signed-off-by: Russell King --- include/asm-arm/arch-pxa/irqs.h | 1 + include/asm-arm/arch-pxa/tosa.h | 44 ++++++++++++++++++++++++++++------------- 2 files changed, 31 insertions(+), 14 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index b6c8fe377683..fa05e76f64e8 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -180,6 +180,7 @@ #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) #elif defined(CONFIG_ARCH_LUBBOCK) || \ defined(CONFIG_MACH_LOGICPD_PXA270) || \ + defined(CONFIG_MACH_TOSA) || \ defined(CONFIG_MACH_MAINSTONE) || \ defined(CONFIG_MACH_PCM027) || \ defined(CONFIG_MACH_MAGICIAN) diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h index 188226216154..a16c103b7251 100644 --- a/include/asm-arm/arch-pxa/tosa.h +++ b/include/asm-arm/arch-pxa/tosa.h @@ -25,7 +25,7 @@ */ #define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 -#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 +#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1) #define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) #define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) #define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) @@ -35,11 +35,9 @@ #define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 /* GPIO Direction 1 : output mode / 0:input mode */ -#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ +#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \ TOSA_SCOOP_AUD_PWR_ON |\ - TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN ) -/* GPIO out put level when init 1: Hi */ -#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN ) + TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN) /* * SCOOP2 jacket GPIOs @@ -49,16 +47,34 @@ #define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) #define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) #define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3) -#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 -#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 +#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4) +#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5) #define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 #define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7) #define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 /* GPIO Direction 1 : output mode / 0:input mode */ -#define TOSA_SCOOP_JC_IO_DIR ( \ - TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ - TOSA_SCOOP_JC_CARD_LIMIT_SEL ) +#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL) + +/* + * TC6393XB GPIOs + */ +#define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12) +#define TOSA_TC6393XB_GPIO(i) (TOSA_TC6393XB_GPIO_BASE + (i)) +#define TOSA_TC6393XB_GPIO_BIT(gpio) (1 << (gpio - TOSA_TC6393XB_GPIO_BASE)) + +#define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0) +#define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1) +#define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3) +#define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4) +#define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6) +#define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7) +#define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9) +#define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10) +#define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11) +#define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12) +#define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14) +#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15) /* * Timing Generator @@ -84,13 +100,13 @@ #define TOSA_GPIO_JACKET_DETECT (7) #define TOSA_GPIO_nSD_DETECT (9) #define TOSA_GPIO_nSD_INT (10) -#define TOSA_GPIO_TC6393_CLK (11) +#define TOSA_GPIO_TC6393XB_CLK (11) #define TOSA_GPIO_BAT1_CRG (12) #define TOSA_GPIO_CF_CD (13) #define TOSA_GPIO_BAT0_CRG (14) -#define TOSA_GPIO_TC6393_INT (15) +#define TOSA_GPIO_TC6393XB_INT (15) #define TOSA_GPIO_BAT0_LOW (17) -#define TOSA_GPIO_TC6393_RDY (18) +#define TOSA_GPIO_TC6393XB_RDY (18) #define TOSA_GPIO_ON_RESET (19) #define TOSA_GPIO_EAR_IN (20) #define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ @@ -138,7 +154,7 @@ #define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) #define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) #define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) -#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT) +#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT) #define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) #define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) #define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) -- cgit v1.2.1 From 16b32fd0a35b30cbd67395cfcbd360354db44f39 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 5 Jul 2008 09:02:48 +0100 Subject: [ARM] 5150/1: Tosa: support built-in bluetooth power-up The driver is pretty much generic and will be later shared with a few other devices, like hx4700 ipaq. Signed-off-by: Dmitry Baryshkov Signed-off-by: Russell King --- include/asm-arm/arch-pxa/tosa.h | 7 +++---- include/asm-arm/arch-pxa/tosa_bt.h | 22 ++++++++++++++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-) create mode 100644 include/asm-arm/arch-pxa/tosa_bt.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h index a16c103b7251..a72803f0461b 100644 --- a/include/asm-arm/arch-pxa/tosa.h +++ b/include/asm-arm/arch-pxa/tosa.h @@ -30,14 +30,13 @@ #define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) #define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) #define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 -#define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17 -#define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18 +#define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6) +#define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7) #define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 /* GPIO Direction 1 : output mode / 0:input mode */ #define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \ - TOSA_SCOOP_AUD_PWR_ON |\ - TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN) + TOSA_SCOOP_AUD_PWR_ON) /* * SCOOP2 jacket GPIOs diff --git a/include/asm-arm/arch-pxa/tosa_bt.h b/include/asm-arm/arch-pxa/tosa_bt.h new file mode 100644 index 000000000000..efc3c3d3b75d --- /dev/null +++ b/include/asm-arm/arch-pxa/tosa_bt.h @@ -0,0 +1,22 @@ +/* + * Tosa bluetooth built-in chip control. + * + * Later it may be shared with some other platforms. + * + * Copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef TOSA_BT_H +#define TOSA_BT_H + +struct tosa_bt_data { + int gpio_pwr; + int gpio_reset; +}; + +#endif + -- cgit v1.2.1 From ff7b04796d9866327ea76e1393f1e902ef032f84 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Tue, 8 Jul 2008 11:58:36 -0700 Subject: dmaengine: DMA engine driver for Marvell XOR engine The XOR engine found in Marvell's SoCs and system controllers provides XOR and DMA operation, iSCSI CRC32C calculation, memory initialization, and memory ECC error cleanup operation support. This driver implements the DMA engine API and supports the following capabilities: - memcpy - xor - memset The XOR engine can be used by DMA engine clients implemented in the kernel, one of those clients is the RAID module. In that case, I observed 20% improvement in the raid5 write throughput, and 40% decrease in the CPU utilization when doing array construction, those results obtained on an 5182 running at 500Mhz. When enabling the NET DMA client, the performance decreased, so meanwhile it is recommended to keep this client off. Signed-off-by: Saeed Bishara Signed-off-by: Lennert Buytenhek Signed-off-by: Nicolas Pitre Acked-by: Maciej Sosnowski Signed-off-by: Dan Williams --- include/asm-arm/plat-orion/mv_xor.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 include/asm-arm/plat-orion/mv_xor.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/plat-orion/mv_xor.h b/include/asm-arm/plat-orion/mv_xor.h new file mode 100644 index 000000000000..c349e8ff5cc0 --- /dev/null +++ b/include/asm-arm/plat-orion/mv_xor.h @@ -0,0 +1,28 @@ +/* + * Marvell XOR platform device data definition file. + */ + +#ifndef __ASM_PLAT_ORION_MV_XOR_H +#define __ASM_PLAT_ORION_MV_XOR_H + +#include +#include + +#define MV_XOR_SHARED_NAME "mv_xor_shared" +#define MV_XOR_NAME "mv_xor" + +struct mbus_dram_target_info; + +struct mv_xor_platform_shared_data { + struct mbus_dram_target_info *dram; +}; + +struct mv_xor_platform_data { + struct platform_device *shared; + int hw_id; + dma_cap_mask_t cap_mask; + size_t pool_size; +}; + + +#endif -- cgit v1.2.1 From e172274ccc55d20536fbdceb6131f38e288541e0 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 13 Jun 2008 09:17:31 +0100 Subject: [ARM] 5088/3: pxa2xx: add pxa2xx_set_spi_info to register pxa2xx-spi platform devices Add a function to dynamically allocate and register pxa2xx-spi platform devices, to be used by PXA2xx and PXA3xx based systems. Switch pcm027 and lubbock to use it. Signed-off-by: Guennadi Liakhovetski Acked-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/pxa2xx_spi.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h index 3459fb26ce97..2206cb61a9f9 100644 --- a/include/asm-arm/arch-pxa/pxa2xx_spi.h +++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h @@ -41,4 +41,6 @@ struct pxa2xx_spi_chip { void (*cs_control)(u32 command); }; +extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); + #endif /*PXA2XX_SPI_H_*/ -- cgit v1.2.1 From 839257c9a818c81a802fdd705602589355571662 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Tue, 17 Jun 2008 09:49:27 +0100 Subject: [ARM] 5106/1: CM-X270: remove unneeded cm-x270.h The include/asm-arm/arch-pxa/cm-x270.h is not used anymore. Remove it. Signed-off-by: Mike Rapoport Signed-off-by: Russell King --- include/asm-arm/arch-pxa/cm-x270.h | 50 -------------------------------------- 1 file changed, 50 deletions(-) delete mode 100644 include/asm-arm/arch-pxa/cm-x270.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h deleted file mode 100644 index f8fac9e18009..000000000000 --- a/include/asm-arm/arch-pxa/cm-x270.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * linux/include/asm/arch-pxa/cm-x270.h - * - * Copyright Compulab Ltd., 2003, 2007 - * Mike Rapoport - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - -/* CM-x270 device physical addresses */ -#define CMX270_CS1_PHYS (PXA_CS1_PHYS) -#define MARATHON_PHYS (PXA_CS2_PHYS) -#define CMX270_IDE104_PHYS (PXA_CS3_PHYS) -#define CMX270_IT8152_PHYS (PXA_CS4_PHYS) - -/* Statically mapped regions */ -#define CMX270_VIRT_BASE (0xe8000000) -#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE) -#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M) - -/* GPIO related definitions */ -#define GPIO_IT8152_IRQ (22) - -#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ) -#define PME_IRQ IRQ_GPIO(0) -#define CMX270_IDE_IRQ IRQ_GPIO(100) -#define CMX270_GPIRQ1 IRQ_GPIO(101) -#define CMX270_TOUCHIRQ IRQ_GPIO(96) -#define CMX270_ETHIRQ IRQ_GPIO(10) -#define CMX270_GFXIRQ IRQ_GPIO(95) -#define CMX270_NANDIRQ IRQ_GPIO(89) -#define CMX270_MMC_IRQ IRQ_GPIO(83) - -/* PCMCIA related definitions */ -#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x))) -#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x))) - -#define PCMCIA_S0_CD_VALID IRQ_GPIO(84) -#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES - -#define PCMCIA_S1_CD_VALID IRQ_GPIO(83) -#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES - -#define PCMCIA_S0_RDYINT IRQ_GPIO(82) -#define PCMCIA_S1_RDYINT IRQ_GPIO(81) - -#define PCMCIA_RESET_GPIO 53 -- cgit v1.2.1 From 6d3dfe4a3141476a3cf59ce6d2d1c25f9b5cfae8 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 2 Jun 2008 15:58:03 +0800 Subject: [ARM] pxa: allow display of uncompress message through STUART Some boards use UART other than FFUART for the console, E.g. Marvell PXA3xx Form Factor Platform (aka Littleton) uses STUART. This patch modifies the uncompress.h so that display of the uncompress message is routed to the STUART. Signed-off-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/uncompress.h | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h index dadf4c20b622..f4551269aaf2 100644 --- a/include/asm-arm/arch-pxa/uncompress.h +++ b/include/asm-arm/arch-pxa/uncompress.h @@ -11,11 +11,11 @@ #include #include +#include -#define __REG(x) ((volatile unsigned long *)x) - -#define UART FFUART +#define __REG(x) ((volatile unsigned long *)x) +static volatile unsigned long *UART = FFUART; static inline void putc(char c) { @@ -33,8 +33,13 @@ static inline void flush(void) { } +static inline void arch_decomp_setup(void) +{ + if (machine_is_littleton()) + UART = STUART; +} + /* * nothing to do */ -#define arch_decomp_setup() #define arch_decomp_wdog() -- cgit v1.2.1 From 566b450c33ea43f339d54d445f4ea1ab2e021909 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 16 Jun 2008 09:47:47 +0800 Subject: [ARM] pxa: add pxa2xx_mfp_set_lpm() to facilitate low power state change Some boards want to change low power state of pins on-the-fly, this function helps to facilitate that operation instead of switching back-n-forth between two configurations with pxa2xx_mfp_config(). Signed-off-by: Eric Miao Tested-by: Robert Jarzmik Signed-off-by: Russell King --- include/asm-arm/arch-pxa/mfp-pxa2xx.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h index db8d890d237c..8de1c0dae624 100644 --- a/include/asm-arm/arch-pxa/mfp-pxa2xx.h +++ b/include/asm-arm/arch-pxa/mfp-pxa2xx.h @@ -128,5 +128,6 @@ #define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); +extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm); extern int gpio_set_wake(unsigned int gpio, unsigned int on); #endif /* __ASM_ARCH_MFP_PXA2XX_H */ -- cgit v1.2.1 From 9ae819a819b4dfc60ac13dd1f1e1a7eaa3d4a6cb Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 2 Jun 2008 15:22:03 +0800 Subject: [ARM] pxa: add pxa3xx NAND device and clock sources A pxa3xx_set_nand_info() is also introduced to set the PXA3xx NAND driver specific platform_data structure pointer. Signed-off-by: Eric Miao Cc: Sergey Podstavin Signed-off-by: Russell King --- include/asm-arm/arch-pxa/pxa3xx_nand.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/include/asm-arm/arch-pxa/pxa3xx_nand.h index 81a8937486cb..eb4b190b6657 100644 --- a/include/asm-arm/arch-pxa/pxa3xx_nand.h +++ b/include/asm-arm/arch-pxa/pxa3xx_nand.h @@ -15,4 +15,6 @@ struct pxa3xx_nand_platform_data { struct mtd_partition *parts; unsigned int nr_parts; }; + +extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); #endif /* __ASM_ARCH_PXA3XX_NAND_H */ -- cgit v1.2.1 From a1f7fc48c143537e2bf70affee7e8932f5be9bb4 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Wed, 28 May 2008 10:44:16 +0800 Subject: [ARM] pxa: add GPIO expander (PCA9539) support for zylonite And also reserve 32 IRQs for the two GPIO expanders. Signed-off-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/irqs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index b6c8fe377683..d85736048461 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -184,6 +184,8 @@ defined(CONFIG_MACH_PCM027) || \ defined(CONFIG_MACH_MAGICIAN) #define NR_IRQS (IRQ_BOARD_END) +#elif defined(CONFIG_MACH_ZYLONITE) +#define NR_IRQS (IRQ_BOARD_START + 32) #else #define NR_IRQS (IRQ_BOARD_START) #endif -- cgit v1.2.1 From 5c9f50e90e8056fb5a8bdd479ab0591d5dad79a0 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Tue, 17 Jun 2008 19:03:54 +0800 Subject: [ARM] pxa: add simple gpio debug LEDs support for zylonite Signed-off-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/zylonite.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h index de577de8d18c..0d35ca04731e 100644 --- a/include/asm-arm/arch-pxa/zylonite.h +++ b/include/asm-arm/arch-pxa/zylonite.h @@ -16,6 +16,8 @@ struct platform_mmc_slot { extern struct platform_mmc_slot zylonite_mmc_slot[]; extern int gpio_eth_irq; +extern int gpio_debug_led1; +extern int gpio_debug_led2; extern int wm9713_irq; -- cgit v1.2.1 From aa9ae8eb1a917c8794bceef0a8e6ff1f4d7c46de Mon Sep 17 00:00:00 2001 From: Ian Molton Date: Wed, 25 Jun 2008 22:17:16 +0100 Subject: Fix serial broken-ness on PXA250 PXA255 and 26x are the only PXA CPUs with HWUART. This patch prevents bogus initialisation on other models. Signed-off-by: Ian Molton --- include/asm-arm/arch-pxa/hardware.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index d9af6dabc899..b6a8317c2ec4 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -69,6 +69,12 @@ _id == 0x212; \ }) +#define __cpu_is_pxa255(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x2d0; \ + }) + #define __cpu_is_pxa25x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ @@ -76,6 +82,7 @@ }) #else #define __cpu_is_pxa21x(id) (0) +#define __cpu_is_pxa255(id) (0) #define __cpu_is_pxa25x(id) (0) #endif @@ -124,6 +131,11 @@ __cpu_is_pxa21x(read_cpuid_id()); \ }) +#define cpu_is_pxa255() \ + ({ \ + __cpu_is_pxa255(read_cpuid_id()); \ + }) + #define cpu_is_pxa25x() \ ({ \ __cpu_is_pxa25x(read_cpuid_id()); \ -- cgit v1.2.1 From b5e4ad57eeffef0ac274413f83be4ef903719ea4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Va=C5=A1ut?= Date: Mon, 7 Jul 2008 17:25:46 +0100 Subject: [ARM] 5153/1: Add support for PalmTX handheld computer PalmTX is PXA27x based device with wifi, bluetooth, touchscreen, sdio slot, irda, keypad, nand flash, pxa framebuffer, serial and usb gadget interface. Supported by this patch is pxafb, touchscreen, irda, keypad and sdio slot. Signed-off-by: Marek Vasut Signed-off-by: Russell King --- include/asm-arm/arch-pxa/palmtx.h | 106 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 include/asm-arm/arch-pxa/palmtx.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/palmtx.h b/include/asm-arm/arch-pxa/palmtx.h new file mode 100644 index 000000000000..1e8bccbda510 --- /dev/null +++ b/include/asm-arm/arch-pxa/palmtx.h @@ -0,0 +1,106 @@ +/* + * GPIOs and interrupts for Palm T|X Handheld Computer + * + * Based on palmld-gpio.h by Alex Osborne + * + * Authors: Marek Vasut + * Cristiano P. + * Jan Herman <2hp@seznam.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMTX_H_ +#define _INCLUDE_PALMTX_H_ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMTX_GPIO_RESET 1 + +#define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */ +#define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10 +#define GPIO_NR_PALMTX_EARPHONE_DETECT 107 + +/* SD/MMC */ +#define GPIO_NR_PALMTX_SD_DETECT_N 14 +#define GPIO_NR_PALMTX_SD_POWER 114 /* probably */ +#define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */ + +/* TOUCHSCREEN */ +#define GPIO_NR_PALMTX_WM9712_IRQ 27 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMTX_IR_DISABLE 40 + +/* USB */ +#define GPIO_NR_PALMTX_USB_DETECT_N 13 +#define GPIO_NR_PALMTX_USB_POWER 95 +#define GPIO_NR_PALMTX_USB_PULLUP 93 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMTX_BL_POWER 84 +#define GPIO_NR_PALMTX_LCD_POWER 96 + +/* LCD BORDER */ +#define GPIO_NR_PALMTX_BORDER_SWITCH 98 +#define GPIO_NR_PALMTX_BORDER_SELECT 22 + +/* BLUETOOTH */ +#define GPIO_NR_PALMTX_BT_POWER 17 +#define GPIO_NR_PALMTX_BT_RESET 83 + +/* PCMCIA (WiFi) */ +#define GPIO_NR_PALMTX_PCMCIA_POWER1 94 +#define GPIO_NR_PALMTX_PCMCIA_POWER2 108 +#define GPIO_NR_PALMTX_PCMCIA_RESET 79 +#define GPIO_NR_PALMTX_PCMCIA_READY 116 + +/* NAND Flash ... this GPIO may be incorrect! */ +#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 + +/* INTERRUPTS */ +#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N) +#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ) +#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT) +#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET) + +/** HERE ARE INIT VALUES **/ + +/* Various addresses */ +#define PALMTX_PCMCIA_PHYS 0x28000000 +#define PALMTX_PCMCIA_VIRT 0xf0000000 +#define PALMTX_PCMCIA_SIZE 0x100000 + +#define PALMTX_PHYS_RAM_START 0xa0000000 +#define PALMTX_PHYS_IO_START 0x40000000 + +#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ +#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ + +/* TOUCHSCREEN */ +#define AC97_LINK_FRAME 21 + + +/* BATTERY */ +#define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */ +#define PALMTX_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMTX_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMTX_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */ + +#define PALMTX_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMTX_MAX_INTENSITY 0xFE +#define PALMTX_DEFAULT_INTENSITY 0x7E +#define PALMTX_LIMIT_MASK 0x7F +#define PALMTX_PRESCALER 0x3F +#define PALMTX_PERIOD_NS 3500 + +#endif -- cgit v1.2.1 From 00249adc0ebf9bc5e1b7b53dee37601fd7291396 Mon Sep 17 00:00:00 2001 From: Stefan Schmidt Date: Wed, 9 Jul 2008 08:05:42 +0100 Subject: [ARM] 5165/1: pxafb: More LCCR3 depth defines Add missing depth definitions to LCCR3. Signed-off-by: Daniel Ribeiro Acked-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/regs-lcd.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h index f762493f5141..999b2a02ce21 100644 --- a/include/asm-arm/arch-pxa/regs-lcd.h +++ b/include/asm-arm/arch-pxa/regs-lcd.h @@ -24,6 +24,12 @@ #define LCCR3_4BPP (2 << 24) #define LCCR3_8BPP (3 << 24) #define LCCR3_16BPP (4 << 24) +#define LCCR3_18BPP (5 << 24) +#define LCCR3_18BPP_P (6 << 24) +#define LCCR3_19BPP (7 << 24) +#define LCCR3_19BPP_P (1 << 29) +#define LCCR3_24BPP ((1 << 29) | (1 << 24)) +#define LCCR3_25BPP ((1 << 29) | (2 << 24)) #define LCCR3_PDFOR_0 (0 << 30) #define LCCR3_PDFOR_1 (1 << 30) -- cgit v1.2.1 From c1450f156fda8921a55e3f4fe596274278010f31 Mon Sep 17 00:00:00 2001 From: Stefan Schmidt Date: Wed, 9 Jul 2008 08:06:32 +0100 Subject: [ARM] 5164/1: pxafb: Support for RGB666, RGBT666, RGB888 and RGBT888 Add the .depth field to pxafb_mode_info and use it to set pixel data format as 18(RGB666), 19(RGBT666), 24(RGB888) or 25(RGBT888) Signed-off-by: Daniel Ribeiro Acked-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/pxafb.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h index bbd22396841a..daf018d0c604 100644 --- a/include/asm-arm/arch-pxa/pxafb.h +++ b/include/asm-arm/arch-pxa/pxafb.h @@ -71,7 +71,8 @@ struct pxafb_mode_info { u_char bpp; u_int cmap_greyscale:1, - unused:31; + depth:8, + unused:23; /* Parallel Mode Timing */ u_char hsync_len; -- cgit v1.2.1 From 390d452fa1d912b6e76744a34777d7390ab1fa1c Mon Sep 17 00:00:00 2001 From: Stefan Schmidt Date: Wed, 9 Jul 2008 08:07:29 +0100 Subject: [ARM] 5163/1: pxa27x_udc: Allow choosing the bits in UP2OCR_SEOS Allow choosing the bits in UP2OCR_SEOS. Signed-off-by: Daniel Ribeiro Acked-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/pxa27x-udc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h index bc1cf7d0773a..ab1443f8bd89 100644 --- a/include/asm-arm/arch-pxa/pxa27x-udc.h +++ b/include/asm-arm/arch-pxa/pxa27x-udc.h @@ -97,7 +97,7 @@ #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ -#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ +#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */ #define UDCCSN(x) __REG2(0x40600100, (x) << 2) #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ -- cgit v1.2.1 From 54b238469bce3a1b5012b2f0ebf261cf1c53e664 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 19 Jun 2008 03:11:49 +0100 Subject: [ARM] 5113/1: PXA SSP: Additional register definitions for PXA3xx SSP Also add some white space for a little clarity. Signed-off-by: Mark Brown Acked-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/regs-ssp.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h index 0255328c3c18..3c04cde2cf1f 100644 --- a/include/asm-arm/arch-pxa/regs-ssp.h +++ b/include/asm-arm/arch-pxa/regs-ssp.h @@ -20,6 +20,10 @@ #define SSTSS (0x38) /* SSP Timeslot Status */ #define SSACD (0x3C) /* SSP Audio Clock Divider */ +#if defined(CONFIG_PXA3xx) +#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ +#endif + /* Common PXA2xx bits first */ #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ @@ -29,10 +33,12 @@ #define SSCR0_National (0x2 << 4) /* National Microwire */ #define SSCR0_ECS (1 << 6) /* External clock select */ #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ + #if defined(CONFIG_PXA25x) #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ -#elif defined(CONFIG_PXA27x) + +#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ #define SSCR0_EDSS (1 << 20) /* Extended data size select */ @@ -45,6 +51,10 @@ #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ #endif +#if defined(CONFIG_PXA3xx) +#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ +#endif + #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ @@ -109,5 +119,9 @@ #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ +#if defined(CONFIG_PXA3xx) +#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ +#endif + #endif /* __ASM_ARCH_REGS_SSP_H */ -- cgit v1.2.1 From c316f101a10f2681618ffb537ecba6084d5a137e Mon Sep 17 00:00:00 2001 From: Ian Molton Date: Thu, 10 Jul 2008 20:01:07 +0100 Subject: E-series GPIO / IRQ definitions. --- include/asm-arm/arch-pxa/eseries-gpio.h | 50 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-pxa/eseries-irq.h | 27 ++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 include/asm-arm/arch-pxa/eseries-gpio.h create mode 100644 include/asm-arm/arch-pxa/eseries-irq.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/eseries-gpio.h b/include/asm-arm/arch-pxa/eseries-gpio.h new file mode 100644 index 000000000000..4c90b1310270 --- /dev/null +++ b/include/asm-arm/arch-pxa/eseries-gpio.h @@ -0,0 +1,50 @@ +/* + * eseries-gpio.h + * + * Copyright (C) Ian Molton + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/* e-series power button */ +#define GPIO_ESERIES_POWERBTN 0 + +/* UDC GPIO definitions */ +#define GPIO_E7XX_USB_DISC 13 +#define GPIO_E7XX_USB_PULLUP 3 + +#define GPIO_E800_USB_DISC 4 +#define GPIO_E800_USB_PULLUP 84 + +/* e740 PCMCIA GPIO definitions */ +/* Note: PWR1 seems to be inverted */ +#define GPIO_E740_PCMCIA_CD0 8 +#define GPIO_E740_PCMCIA_CD1 44 +#define GPIO_E740_PCMCIA_RDY0 11 +#define GPIO_E740_PCMCIA_RDY1 6 +#define GPIO_E740_PCMCIA_RST0 27 +#define GPIO_E740_PCMCIA_RST1 24 +#define GPIO_E740_PCMCIA_PWR0 20 +#define GPIO_E740_PCMCIA_PWR1 23 + +/* e750 PCMCIA GPIO definitions */ +#define GPIO_E750_PCMCIA_CD0 8 +#define GPIO_E750_PCMCIA_RDY0 12 +#define GPIO_E750_PCMCIA_RST0 27 +#define GPIO_E750_PCMCIA_PWR0 20 + +/* e800 PCMCIA GPIO definitions */ +#define GPIO_E800_PCMCIA_RST0 69 +#define GPIO_E800_PCMCIA_RST1 72 +#define GPIO_E800_PCMCIA_PWR0 20 +#define GPIO_E800_PCMCIA_PWR1 73 + +/* e7xx IrDA power control */ +#define GPIO_E7XX_IR_ON 38 + +/* ASIC related GPIOs */ +#define GPIO_ESERIES_TMIO_IRQ 5 +#define GPIO_E800_ANGELX_IRQ 8 diff --git a/include/asm-arm/arch-pxa/eseries-irq.h b/include/asm-arm/arch-pxa/eseries-irq.h new file mode 100644 index 000000000000..f2a93d5e31d3 --- /dev/null +++ b/include/asm-arm/arch-pxa/eseries-irq.h @@ -0,0 +1,27 @@ +/* + * eseries-irq.h + * + * Copyright (C) Ian Molton + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8) +#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n)) + +#define ANGELX_RDY0_IRQ IRQ_ANGELX(0) +#define ANGELX_ST0_IRQ IRQ_ANGELX(1) +#define ANGELX_CD0_IRQ IRQ_ANGELX(2) +#define ANGELX_RDY1_IRQ IRQ_ANGELX(3) +#define ANGELX_ST1_IRQ IRQ_ANGELX(4) +#define ANGELX_CD1_IRQ IRQ_ANGELX(5) + +#define TMIO_IRQ_BASE (IRQ_BOARD_START+0) +#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n)) + +#define TMIO_SD_IRQ IRQ_TMIO(1) +#define TMIO_USB_IRQ IRQ_TMIO(2) + -- cgit v1.2.1 From 8fb105f5cc7f31ff37755945378a668f4c21590e Mon Sep 17 00:00:00 2001 From: Ian Molton Date: Wed, 25 Jun 2008 22:34:51 +0100 Subject: PXA UDC - allow use of inverted GPIO for pullup Signed-off-by: Ian Molton --- include/asm-arm/mach/udc_pxa2xx.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/mach/udc_pxa2xx.h b/include/asm-arm/mach/udc_pxa2xx.h index f9f3606986c2..9e5ed7c0f27f 100644 --- a/include/asm-arm/mach/udc_pxa2xx.h +++ b/include/asm-arm/mach/udc_pxa2xx.h @@ -23,6 +23,7 @@ struct pxa2xx_udc_mach_info { */ bool gpio_vbus_inverted; u16 gpio_vbus; /* high == vbus present */ + bool gpio_pullup_inverted; u16 gpio_pullup; /* high == pullup activated */ }; -- cgit v1.2.1 From 5d31e43589589e63f5b96abc62372d2ef331c14a Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Fri, 11 Jul 2008 12:45:39 +0800 Subject: [ARM] pxa: add base support for PXA930 (aka Tavor-P) Signed-off-by: Eric Miao Signed-off-by: Russell King --- include/asm-arm/arch-pxa/hardware.h | 16 ++ include/asm-arm/arch-pxa/mfp-pxa930.h | 491 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-pxa/mfp.h | 8 + 3 files changed, 515 insertions(+) create mode 100644 include/asm-arm/arch-pxa/mfp-pxa930.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 09868de841a5..979a45695d7d 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -126,6 +126,16 @@ #define __cpu_is_pxa320(id) (0) #endif +#ifdef CONFIG_CPU_PXA930 +#define __cpu_is_pxa930(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x683; \ + }) +#else +#define __cpu_is_pxa930(id) (0) +#endif + #define cpu_is_pxa21x() \ ({ \ __cpu_is_pxa21x(read_cpuid_id()); \ @@ -161,6 +171,12 @@ __cpu_is_pxa320(read_cpuid_id()); \ }) +#define cpu_is_pxa930() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa930(id); \ + }) + /* * CPUID Core Generation Bit * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x diff --git a/include/asm-arm/arch-pxa/mfp-pxa930.h b/include/asm-arm/arch-pxa/mfp-pxa930.h new file mode 100644 index 000000000000..c4e945ab1923 --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa930.h @@ -0,0 +1,491 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp-pxa930.h + * + * PXA930 specific MFP configuration definitions + * + * Copyright (C) 2007-2008 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA9xx_H +#define __ASM_ARCH_MFP_PXA9xx_H + +#include +#include + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) + +#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0) +#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0) +#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0) +#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0) + +#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0) +#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0) +#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0) +#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0) +#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0) +#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0) +#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0) +#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0) +#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0) +#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0) +#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0) +#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0) +#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0) +#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0) +#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0) +#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0) +#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0) +#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0) +#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0) +#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0) +#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0) +#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0) +#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0) +#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0) +#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0) + +#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0) +#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0) +#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0) +#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0) +#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0) +#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0) +#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0) +#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0) +#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0) +#define RDY_GPIO_62 MFP_CFG(RDY, AF0) + +/* Chip Select */ +#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH) +#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH) + +/* AC97 */ +#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3) +#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3) +#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3) +#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3) +#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3) +#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3) + +/* I2C */ +#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH) +#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH) + +#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH) +#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH) + +#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH) +#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH) + +#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH) +#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH) + +#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH) +#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH) + +#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) + +#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH) +#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH) + +/* QCI */ +#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW) +#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW) +#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW) +#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW) +#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW) +#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW) +#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW) +#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW) +#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW) +#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW) +#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW) +#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW) +#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW) +#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW) + +/* KEYPAD */ +#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT) +#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT) +#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT) +#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT) +#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT) +#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT) +#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT) +#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT) + +#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT) +#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT) +#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT) +#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT) + +#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT) +#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT) +#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT) +#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT) + +#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT) +#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT) +#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT) +#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT) +#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT) +#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT) +#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT) +#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1) +#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4) + +#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH) +#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH) +#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH) +#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) +#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH) +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH) +#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH) +#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH) + +/* LCD */ +#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1) +#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1) +#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1) +#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1) +#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1) +#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2) +#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1) +#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1) +#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1) +#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1) +#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1) +#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1) +#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1) +#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1) +#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1) +#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1) +#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1) +#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1) +#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1) +#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1) +#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1) +#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1) +#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1) +#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1) +#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1) +#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3) +#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3) +#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1) + +/* Mini-LCD */ +#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3) +#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3) +#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3) +#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3) +#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3) +#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3) +#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3) +#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3) +#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3) +#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3) +#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3) +#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3) +#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3) +#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3) +#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3) +#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3) +#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3) +#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3) +#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3) +#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3) +#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5) + +/* MMC1 */ +#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4) +#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4) +#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4) +#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4) +#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4) +#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4) +#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3) +#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3) +#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3) +#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3) +#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3) +#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3) + +#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2) +#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2) +#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2) +#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3) +#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2) + +/* MMC2 */ +#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7) +#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7) +#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7) +#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7) +#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7) +#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7) + +#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1) +#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1) +#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1) +#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1) +#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1) +#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1) + +#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3) +#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3) +#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3) +#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3) +#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3) +#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3) + +/* BSSP1 */ +#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3) +#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3) +#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3) +#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3) +#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5) +#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5) + +/* BSSP2 */ +#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1) +#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1) +#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1) +#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1) +#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1) +#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4) + +/* BSSP3 */ +#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1) +#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1) +#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1) +#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1) +#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1) + +/* BSSP4 */ +#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4) +#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4) +#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4) +#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4) + +#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4) +#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4) +#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4) +#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4) + +/* GSSP1 */ +#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2) +#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2) +#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2) +#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2) +#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2) + +#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4) +#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4) +#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4) +#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4) + +/* GSSP2 */ +#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4) +#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4) +#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4) +#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4) + +#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4) +#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4) +#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4) +#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4) + +#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2) +#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2) +#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2) +#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2) +#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2) +#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5) + +#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2) +#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2) +#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2) +#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2) + +/* UART1 - FFUART */ +#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1) +#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1) +#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1) +#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1) +#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1) +#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1) +#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1) +#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1) + +#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2) +#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2) +#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2) +#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2) +#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2) +#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2) +#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2) +#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2) + +/* UART2 - BTUART */ +#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1) +#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1) +#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1) +#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1) + +/* UART3 - STUART */ +#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3) +#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3) +#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3) +#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3) + +#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5) +#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5) +#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5) +#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5) + +/* DFI */ +#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2) +#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2) +#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2) +#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2) +#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2) +#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2) +#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2) +#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2) +#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2) +#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2) +#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2) +#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2) +#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2) +#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2) +#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2) +#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2) +#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2) +#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2) +#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2) +#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2) +#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2) +#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2) + +/* DFI - NAND */ +#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH) +#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW) +#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW) +#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW) +#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW) +#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW) +#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW) +#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW) +#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW) +#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW) +#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW) +#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW) +#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW) +#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW) +#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW) +#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW) +#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW) +#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW) +#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH) +#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH) +#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH) +#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH) +#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH) +#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH) +#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH) + +/* PWM */ +#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW) +#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW) +#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW) +#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) +#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) +#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) + +/* CIR */ +#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) +#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3) + +/* USB P2 */ +#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3) +#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5) +#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2) +#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7) +#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6) +#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3) + +#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2) +#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT) +#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2) +#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2) +#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2) +#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2) +#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2) +#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2) + +#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3) +#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3) +#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3) +#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3) +#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3) +#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3) +#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3) +#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3) + +/* ULPI */ +#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4) +#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7) +#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5) +#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5) +#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5) +#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5) +#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5) +#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5) +#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4) +#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4) +#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4) +#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4) + +#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3) +#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7) +#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5) +#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4) +#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3) +#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3) + +#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5) +#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7) +#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5) +#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4) + +#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3) +#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7) +#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3) +#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5) +#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4) +#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3) + +/* 1 wire */ +#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5) + +#endif /* __ASM_ARCH_MFP_PXA9xx_H */ diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h index 02f6157396d3..e7d58798da67 100644 --- a/include/asm-arm/arch-pxa/mfp.h +++ b/include/asm-arm/arch-pxa/mfp.h @@ -210,6 +210,14 @@ enum { MFP_PIN_DF_IO14, MFP_PIN_DF_IO15, + /* additional pins on PXA930 */ + MFP_PIN_GSIM_UIO, + MFP_PIN_GSIM_UCLK, + MFP_PIN_GSIM_UDET, + MFP_PIN_GSIM_nURST, + MFP_PIN_PMIC_INT, + MFP_PIN_RDY, + MFP_PIN_MAX, }; -- cgit v1.2.1 From 2a46fa13d788364c093c4296fe01cae837aa8919 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Thu, 17 Jul 2008 17:59:56 -0700 Subject: iop_adma: cleanup iop_chan_xor_slot_count - use a table for iop13xx, trade text for data - shrink the iop3xx to a cache line Signed-off-by: Dan Williams --- include/asm-arm/arch-iop13xx/adma.h | 18 +++++++----------- include/asm-arm/hardware/iop3xx-adma.h | 4 ++-- 2 files changed, 9 insertions(+), 13 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h index 90d14ee564f5..ef4f5da2029f 100644 --- a/include/asm-arm/arch-iop13xx/adma.h +++ b/include/asm-arm/arch-iop13xx/adma.h @@ -198,17 +198,13 @@ iop_chan_memset_slot_count(size_t len, int *slots_per_op) static inline int iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) { - int num_slots; - /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1 - * (1 source => 8 bytes) (1 slot => 32 bytes) - */ - num_slots = 1 + (((src_cnt - 1) << 3) >> 5); - if (((src_cnt - 1) << 3) & 0x1f) - num_slots++; - - *slots_per_op = num_slots; - - return num_slots; + static const char slot_count_table[] = { 1, 2, 2, 2, + 2, 3, 3, 3, + 3, 4, 4, 4, + 4, 5, 5, 5, + }; + *slots_per_op = slot_count_table[src_cnt - 1]; + return *slots_per_op; } #define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h index a32b86ac62aa..af64676650a2 100644 --- a/include/asm-arm/hardware/iop3xx-adma.h +++ b/include/asm-arm/hardware/iop3xx-adma.h @@ -260,7 +260,7 @@ static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op) static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) { - static const int slot_count_table[] = { 0, + static const char slot_count_table[] = { 1, 1, 1, 1, /* 01 - 04 */ 2, 2, 2, 2, /* 05 - 08 */ 4, 4, 4, 4, /* 09 - 12 */ @@ -270,7 +270,7 @@ static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, 8, 8, 8, 8, /* 25 - 28 */ 8, 8, 8, 8, /* 29 - 32 */ }; - *slots_per_op = slot_count_table[src_cnt]; + *slots_per_op = slot_count_table[src_cnt - 1]; return *slots_per_op; } -- cgit v1.2.1 From 5cbad0ebf45c5417104b383dc0e34f64fa7f2473 Mon Sep 17 00:00:00 2001 From: Jason Wessel Date: Wed, 20 Feb 2008 13:33:40 -0600 Subject: kgdb: support for ARCH=arm This patch adds the ARCH=arm specific a kgdb backend, originally written by Deepak Saxena and George Davis . Geoff Levand , Nicolas Pitre, Manish Lachwani, and Jason Wessel have contributed various fixups here as well. The KGDB patch makes one change to the core ARM architecture such that the traps are initialized early for use with the debugger or other subsystems. [ mingo@elte.hu: small cleanups. ] [ ben-linux@fluff.org: fixed early_trap_init ] Signed-off-by: Jason Wessel Acked-by: Deepak Saxena --- include/asm-arm/kgdb.h | 104 ++++++++++++++++++++++++++++++++++++++++++++++++ include/asm-arm/traps.h | 2 + 2 files changed, 106 insertions(+) create mode 100644 include/asm-arm/kgdb.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/kgdb.h b/include/asm-arm/kgdb.h new file mode 100644 index 000000000000..67af4b841984 --- /dev/null +++ b/include/asm-arm/kgdb.h @@ -0,0 +1,104 @@ +/* + * ARM KGDB support + * + * Author: Deepak Saxena + * + * Copyright (C) 2002 MontaVista Software Inc. + * + */ + +#ifndef __ARM_KGDB_H__ +#define __ARM_KGDB_H__ + +#include + +/* + * GDB assumes that we're a user process being debugged, so + * it will send us an SWI command to write into memory as the + * debug trap. When an SWI occurs, the next instruction addr is + * placed into R14_svc before jumping to the vector trap. + * This doesn't work for kernel debugging as we are already in SVC + * we would loose the kernel's LR, which is a bad thing. This + * is bad thing. + * + * By doing this as an undefined instruction trap, we force a mode + * switch from SVC to UND mode, allowing us to save full kernel state. + * + * We also define a KGDB_COMPILED_BREAK which can be used to compile + * in breakpoints. This is important for things like sysrq-G and for + * the initial breakpoint from trap_init(). + * + * Note to ARM HW designers: Add real trap support like SH && PPC to + * make our lives much much simpler. :) + */ +#define BREAK_INSTR_SIZE 4 +#define GDB_BREAKINST 0xef9f0001 +#define KGDB_BREAKINST 0xe7ffdefe +#define KGDB_COMPILED_BREAK 0xe7ffdeff +#define CACHE_FLUSH_IS_SAFE 1 + +#ifndef __ASSEMBLY__ + +static inline void arch_kgdb_breakpoint(void) +{ + asm(".word 0xe7ffdeff"); +} + +extern void kgdb_handle_bus_error(void); +extern int kgdb_fault_expected; + +#endif /* !__ASSEMBLY__ */ + +/* + * From Kevin Hilman: + * + * gdb is expecting the following registers layout. + * + * r0-r15: 1 long word each + * f0-f7: unused, 3 long words each !! + * fps: unused, 1 long word + * cpsr: 1 long word + * + * Even though f0-f7 and fps are not used, they need to be + * present in the registers sent for correct processing in + * the host-side gdb. + * + * In particular, it is crucial that CPSR is in the right place, + * otherwise gdb will not be able to correctly interpret stepping over + * conditional branches. + */ +#define _GP_REGS 16 +#define _FP_REGS 8 +#define _EXTRA_REGS 2 +#define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS) + +#define KGDB_MAX_NO_CPUS 1 +#define BUFMAX 400 +#define NUMREGBYTES (GDB_MAX_REGS << 2) +#define NUMCRITREGBYTES (32 << 2) + +#define _R0 0 +#define _R1 1 +#define _R2 2 +#define _R3 3 +#define _R4 4 +#define _R5 5 +#define _R6 6 +#define _R7 7 +#define _R8 8 +#define _R9 9 +#define _R10 10 +#define _FP 11 +#define _IP 12 +#define _SPT 13 +#define _LR 14 +#define _PC 15 +#define _CPSR (GDB_MAX_REGS - 1) + +/* + * So that we can denote the end of a frame for tracing, + * in the simple case: + */ +#define CFI_END_FRAME(func) __CFI_END_FRAME(_PC, _SPT, func) + +#endif /* __ASM_KGDB_H__ */ diff --git a/include/asm-arm/traps.h b/include/asm-arm/traps.h index f1541afcf85c..aa399aec568e 100644 --- a/include/asm-arm/traps.h +++ b/include/asm-arm/traps.h @@ -24,4 +24,6 @@ static inline int in_exception_text(unsigned long ptr) ptr < (unsigned long)&__exception_text_end; } +extern void __init early_trap_init(void); + #endif -- cgit v1.2.1 From 2351ec533ed0dd56052ab96988d2161d5ecc8ed9 Mon Sep 17 00:00:00 2001 From: Matthew Wilcox Date: Thu, 24 Jul 2008 08:09:32 -0400 Subject: Remove asm/semaphore.h All users have now been converted to linux/semaphore.h and we don't need to keep these files around any longer. Signed-off-by: Matthew Wilcox --- include/asm-arm/semaphore.h | 1 - 1 file changed, 1 deletion(-) delete mode 100644 include/asm-arm/semaphore.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h deleted file mode 100644 index d9b2034ed1d2..000000000000 --- a/include/asm-arm/semaphore.h +++ /dev/null @@ -1 +0,0 @@ -#include -- cgit v1.2.1 From 27ac792ca0b0a1e7e65f20342260650516c95864 Mon Sep 17 00:00:00 2001 From: Andrea Righi Date: Wed, 23 Jul 2008 21:28:13 -0700 Subject: PAGE_ALIGN(): correctly handle 64-bit values on 32-bit architectures On 32-bit architectures PAGE_ALIGN() truncates 64-bit values to the 32-bit boundary. For example: u64 val = PAGE_ALIGN(size); always returns a value < 4GB even if size is greater than 4GB. The problem resides in PAGE_MASK definition (from include/asm-x86/page.h for example): #define PAGE_SHIFT 12 #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) ... #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) The "~" is performed on a 32-bit value, so everything in "and" with PAGE_MASK greater than 4GB will be truncated to the 32-bit boundary. Using the ALIGN() macro seems to be the right way, because it uses typeof(addr) for the mask. Also move the PAGE_ALIGN() definitions out of include/asm-*/page.h in include/linux/mm.h. See also lkml discussion: http://lkml.org/lkml/2008/6/11/237 [akpm@linux-foundation.org: fix drivers/media/video/uvc/uvc_queue.c] [akpm@linux-foundation.org: fix v850] [akpm@linux-foundation.org: fix powerpc] [akpm@linux-foundation.org: fix arm] [akpm@linux-foundation.org: fix mips] [akpm@linux-foundation.org: fix drivers/media/video/pvrusb2/pvrusb2-dvb.c] [akpm@linux-foundation.org: fix drivers/mtd/maps/uclinux.c] [akpm@linux-foundation.org: fix powerpc] Signed-off-by: Andrea Righi Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-arm/page-nommu.h | 4 +--- include/asm-arm/page.h | 3 --- 2 files changed, 1 insertion(+), 6 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/page-nommu.h b/include/asm-arm/page-nommu.h index a1bcad060480..ea1cde84f500 100644 --- a/include/asm-arm/page-nommu.h +++ b/include/asm-arm/page-nommu.h @@ -7,6 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ + #ifndef _ASMARM_PAGE_NOMMU_H #define _ASMARM_PAGE_NOMMU_H @@ -42,9 +43,6 @@ typedef unsigned long pgprot_t; #define __pmd(x) (x) #define __pgprot(x) (x) -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) - extern unsigned long memory_start; extern unsigned long memory_end; diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h index 8e05bdb5f12f..7c5fc5582e5d 100644 --- a/include/asm-arm/page.h +++ b/include/asm-arm/page.h @@ -15,9 +15,6 @@ #define PAGE_SIZE (1UL << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) - #ifndef __ASSEMBLY__ #ifndef CONFIG_MMU -- cgit v1.2.1 From e7ecb331e11d1f7aa66aeef9170fc20781c9bb55 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Wed, 23 Jul 2008 21:28:35 -0700 Subject: pm: remove remaining obsolete definitions from pm.h Remove the remaining obsolete definitions from include/linux/pm.h and move the definitions of PM_SUSPEND and PM_RESUME to the header of h3600 which is the only user of them. Signed-off-by: Rafael J. Wysocki Acked-by: Pavel Machek Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-arm/arch-sa1100/h3600.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-sa1100/h3600.h b/include/asm-arm/arch-sa1100/h3600.h index 1b6355971574..3ca0ecf095e6 100644 --- a/include/asm-arm/arch-sa1100/h3600.h +++ b/include/asm-arm/arch-sa1100/h3600.h @@ -23,6 +23,11 @@ #ifndef _INCLUDE_H3600_H_ #define _INCLUDE_H3600_H_ +typedef int __bitwise pm_request_t; + +#define PM_SUSPEND ((__force pm_request_t) 1) /* enter D1-D3 */ +#define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ + /* generalized support for H3xxx series Compaq Pocket PC's */ #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) -- cgit v1.2.1 From d83b8b85cd56a083d30df73f3fd5e4714591b910 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Thu, 24 Jul 2008 22:53:30 +0200 Subject: ide: define MAX_HWIFS in * Now that ide_hwif_t instances are allocated dynamically the difference between MAX_HWIFS == 2 and MAX_HWIFS == 10 is ~100 bytes (x86-32) so use MAX_HWIFS == 10 on all archs except these ones that use MAX_HWIFS == 1. * Define MAX_HWIFS in instead of . [ Please note that avr32/cris/v850 have no and alpha/ia64/sh always define CONFIG_IDE_MAX_HWIFS. ] Signed-off-by: Bartlomiej Zolnierkiewicz --- include/asm-arm/ide.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/ide.h b/include/asm-arm/ide.h index 88f4d231ce4f..a48019f99d08 100644 --- a/include/asm-arm/ide.h +++ b/include/asm-arm/ide.h @@ -13,10 +13,6 @@ #ifdef __KERNEL__ -#ifndef MAX_HWIFS -#define MAX_HWIFS 4 -#endif - #define __ide_mm_insw(port,addr,len) readsw(port,addr,len) #define __ide_mm_insl(port,addr,len) readsl(port,addr,len) #define __ide_mm_outsw(port,addr,len) writesw(port,addr,len) -- cgit v1.2.1 From b69c49b78457f681ecfb3147bd968434ee6559c1 Mon Sep 17 00:00:00 2001 From: FUJITA Tomonori Date: Fri, 25 Jul 2008 01:45:40 -0700 Subject: clean up duplicated alloc/free_thread_info We duplicate alloc/free_thread_info defines on many platforms (the majority uses __get_free_pages/free_pages). This patch defines common defines and removes these duplicated defines. __HAVE_ARCH_THREAD_INFO_ALLOCATOR is introduced for platforms that do something different. Signed-off-by: FUJITA Tomonori Acked-by: Russell King Cc: Pekka Enberg Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-arm/thread_info.h | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index f5a664786311..d4be2d646160 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -97,19 +97,6 @@ static inline struct thread_info *current_thread_info(void) return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); } -/* thread information allocation */ -#ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) \ - ((struct thread_info *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, \ - THREAD_SIZE_ORDER)) -#else -#define alloc_thread_info(tsk) \ - ((struct thread_info *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER)) -#endif - -#define free_thread_info(info) \ - free_pages((unsigned long)info, THREAD_SIZE_ORDER); - #define thread_saved_pc(tsk) \ ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc))) #define thread_saved_fp(tsk) \ -- cgit v1.2.1 From f22ab814a24e654b1de24db0c5f8b57b5ab2026a Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Fri, 25 Jul 2008 01:47:34 -0700 Subject: include/asm/ptrace.h userspace headers cleanup This patch contains the following cleanups for the asm/ptrace.h userspace headers: - include/asm-generic/Kbuild.asm already lists ptrace.h, remove the superfluous listings in the Kbuild files of the following architectures: - cris - frv - powerpc - x86 - don't expose function prototypes and macros to userspace: - arm - blackfin - cris - mn10300 - parisc - remove #ifdef CONFIG_'s around #define's: - blackfin - m68knommu - sh: AFAIK __SH5__ should work in both kernel and userspace, no need to leak CONFIG_SUPERH64 to userspace - xtensa: cosmetical change to remove empty #ifndef __ASSEMBLY__ #else #endif from the userspace headers Not changed by this patch is the fact that the following architectures have a different struct pt_regs depending on CONFIG_ variables: - h8300 - m68knommu - mips This does not work in userspace. Signed-off-by: Adrian Bunk Cc: Cc: Roland McGrath Cc: Oleg Nesterov Acked-by: Greg Ungerer Acked-by: Paul Mundt Acked-by: Grant Grundler Acked-by: Jesper Nilsson Acked-by: Chris Zankel Acked-by: David Howells Acked-by: Paul Mackerras Acked-by: Russell King Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-arm/ptrace.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h index 7aaa206cb54e..8382b7510f94 100644 --- a/include/asm-arm/ptrace.h +++ b/include/asm-arm/ptrace.h @@ -139,8 +139,6 @@ static inline int valid_user_regs(struct pt_regs *regs) return 0; } -#endif /* __KERNEL__ */ - #define pc_pointer(v) \ ((v) & ~PCMASK) @@ -153,10 +151,10 @@ extern unsigned long profile_pc(struct pt_regs *regs); #define profile_pc(regs) instruction_pointer(regs) #endif -#ifdef __KERNEL__ #define predicate(x) ((x) & 0xf0000000) #define PREDICATE_ALWAYS 0xe0000000 -#endif + +#endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ -- cgit v1.2.1 From 7dcf2a9fced59e58e4694cdcf15850c01fdba89b Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Tue, 1 Jul 2008 19:27:16 +0300 Subject: remove dummy asm/kvm.h files This patch removes the dummy asm/kvm.h files on architectures not (yet) supporting KVM and uses the same conditional headers installation as already used for a.out.h . Also removed are superfluous install rules in the s390 and x86 Kbuild files (they are already in Kbuild.asm). Signed-off-by: Adrian Bunk Acked-by: Sam Ravnborg Signed-off-by: David Woodhouse --- include/asm-arm/kvm.h | 6 ------ 1 file changed, 6 deletions(-) delete mode 100644 include/asm-arm/kvm.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/kvm.h b/include/asm-arm/kvm.h deleted file mode 100644 index cb3c08cbcb9e..000000000000 --- a/include/asm-arm/kvm.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __LINUX_KVM_ARM_H -#define __LINUX_KVM_ARM_H - -/* arm does not support KVM */ - -#endif -- cgit v1.2.1 From 0c65f459ce6c8bd873a61b3ae1e57858ab1debf3 Mon Sep 17 00:00:00 2001 From: Andrew Morton Date: Wed, 23 Jul 2008 15:35:22 -0700 Subject: [ARM] fix fls() for 64-bit arguments arm's fls() is implemented as a macro, causing it to misbehave when passed 64-bit arguments. Fix. Cc: Nickolay Vinogradov Tested-by: Krzysztof Halasa Cc: Signed-off-by: Andrew Morton Signed-off-by: Russell King --- include/asm-arm/bitops.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 5c60bfc1a84d..9a1db20e032a 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -277,9 +277,16 @@ static inline int constant_fls(int x) * the clz instruction for much better code efficiency. */ -#define fls(x) \ +#define __fls(x) \ ( __builtin_constant_p(x) ? constant_fls(x) : \ ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) ) + +/* Implement fls() in C so that 64-bit args are suitably truncated */ +static inline int fls(int x) +{ + return __fls(x); +} + #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) #define __ffs(x) (ffs(x) - 1) #define ffz(x) __ffs( ~(x) ) -- cgit v1.2.1 From dd438e77f01d024919a8ae81d0cf2e4c6cda79cc Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 25 Jul 2008 20:55:52 +0100 Subject: [ARM] pci: provide dummy pci_get_legacy_ide_irq() This fixes footbridge_defconfig: drivers/pnp/resource.c: In function 'pci_dev_uses_irq': drivers/pnp/resource.c:317: error: implicit declaration of function 'pci_get_legacy_ide_irq' Signed-off-by: Russell King --- include/asm-arm/pci.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h index 75feb1574a69..2d84792f2e12 100644 --- a/include/asm-arm/pci.h +++ b/include/asm-arm/pci.h @@ -78,6 +78,14 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } +/* + * Dummy implementation; always return 0. + */ +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) +{ + return 0; +} + #endif /* __KERNEL__ */ #endif -- cgit v1.2.1 From 8d8bb39b9eba32dd70e87fd5ad5c5dd4ba118e06 Mon Sep 17 00:00:00 2001 From: FUJITA Tomonori Date: Fri, 25 Jul 2008 19:44:49 -0700 Subject: dma-mapping: add the device argument to dma_mapping_error() Add per-device dma_mapping_ops support for CONFIG_X86_64 as POWER architecture does: This enables us to cleanly fix the Calgary IOMMU issue that some devices are not behind the IOMMU (http://lkml.org/lkml/2008/5/8/423). I think that per-device dma_mapping_ops support would be also helpful for KVM people to support PCI passthrough but Andi thinks that this makes it difficult to support the PCI passthrough (see the above thread). So I CC'ed this to KVM camp. Comments are appreciated. A pointer to dma_mapping_ops to struct dev_archdata is added. If the pointer is non NULL, DMA operations in asm/dma-mapping.h use it. If it's NULL, the system-wide dma_ops pointer is used as before. If it's useful for KVM people, I plan to implement a mechanism to register a hook called when a new pci (or dma capable) device is created (it works with hot plugging). It enables IOMMUs to set up an appropriate dma_mapping_ops per device. The major obstacle is that dma_mapping_error doesn't take a pointer to the device unlike other DMA operations. So x86 can't have dma_mapping_ops per device. Note all the POWER IOMMUs use the same dma_mapping_error function so this is not a problem for POWER but x86 IOMMUs use different dma_mapping_error functions. The first patch adds the device argument to dma_mapping_error. The patch is trivial but large since it touches lots of drivers and dma-mapping.h in all the architecture. This patch: dma_mapping_error() doesn't take a pointer to the device unlike other DMA operations. So we can't have dma_mapping_ops per device. Note that POWER already has dma_mapping_ops per device but all the POWER IOMMUs use the same dma_mapping_error function. x86 IOMMUs use device argument. [akpm@linux-foundation.org: fix sge] [akpm@linux-foundation.org: fix svc_rdma] [akpm@linux-foundation.org: build fix] [akpm@linux-foundation.org: fix bnx2x] [akpm@linux-foundation.org: fix s2io] [akpm@linux-foundation.org: fix pasemi_mac] [akpm@linux-foundation.org: fix sdhci] [akpm@linux-foundation.org: build fix] [akpm@linux-foundation.org: fix sparc] [akpm@linux-foundation.org: fix ibmvscsi] Signed-off-by: FUJITA Tomonori Cc: Muli Ben-Yehuda Cc: Andi Kleen Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Avi Kivity Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-arm/dma-mapping.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h index e99406a7bece..f41335ba6337 100644 --- a/include/asm-arm/dma-mapping.h +++ b/include/asm-arm/dma-mapping.h @@ -56,7 +56,7 @@ static inline int dma_is_consistent(struct device *dev, dma_addr_t handle) /* * DMA errors are defined by all-bits-set in the DMA address. */ -static inline int dma_mapping_error(dma_addr_t dma_addr) +static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { return dma_addr == ~0; } -- cgit v1.2.1 From 19fd6231279be3c3bdd02ed99f9b0eb195978064 Mon Sep 17 00:00:00 2001 From: Nick Piggin Date: Fri, 25 Jul 2008 19:45:32 -0700 Subject: mm: spinlock tree_lock mapping->tree_lock has no read lockers. convert the lock from an rwlock to a spinlock. Signed-off-by: Nick Piggin Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Hugh Dickins Cc: "Paul E. McKenney" Reviewed-by: Peter Zijlstra Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-arm/cacheflush.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 70b0fe724b62..03cf1ee977b7 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -424,9 +424,9 @@ static inline void flush_anon_page(struct vm_area_struct *vma, } #define flush_dcache_mmap_lock(mapping) \ - write_lock_irq(&(mapping)->tree_lock) + spin_lock_irq(&(mapping)->tree_lock) #define flush_dcache_mmap_unlock(mapping) \ - write_unlock_irq(&(mapping)->tree_lock) + spin_unlock_irq(&(mapping)->tree_lock) #define flush_icache_user_range(vma,page,addr,len) \ flush_dcache_page(page) -- cgit v1.2.1 From aafe0ad81d7458b6c61eeb39068432683c70c9a9 Mon Sep 17 00:00:00 2001 From: Ian Molton Date: Sat, 12 Jul 2008 11:55:42 +0100 Subject: [ARM] pxa: PXA25x UDC - Fix warning during build Fixes an unterminated ' warning building PXA25X UDC. Signed-off-by: Ian Molton --- include/asm-arm/arch-pxa/pxa25x-udc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h index 840305916b6d..1b80a4805a60 100644 --- a/include/asm-arm/arch-pxa/pxa25x-udc.h +++ b/include/asm-arm/arch-pxa/pxa25x-udc.h @@ -2,7 +2,7 @@ #define _ASM_ARCH_PXA25X_UDC_H #ifdef _ASM_ARCH_PXA27X_UDC_H -#error You can't include both PXA25x and PXA27x UDC support +#error "You can't include both PXA25x and PXA27x UDC support" #endif #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ -- cgit v1.2.1 From 7f2da1e7d0330395e5e9e350b879b98a1ea495df Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 10 May 2008 20:44:54 -0400 Subject: [PATCH] kill altroot long overdue... Signed-off-by: Al Viro --- include/asm-arm/namei.h | 25 ------------------------- 1 file changed, 25 deletions(-) delete mode 100644 include/asm-arm/namei.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/namei.h b/include/asm-arm/namei.h deleted file mode 100644 index a402d3b9d0f7..000000000000 --- a/include/asm-arm/namei.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * linux/include/asm-arm/namei.h - * - * Routines to handle famous /usr/gnemul - * Derived from the Sparc version of this file - * - * Included from linux/fs/namei.c - */ - -#ifndef __ASMARM_NAMEI_H -#define __ASMARM_NAMEI_H - -#define ARM_BSD_EMUL "usr/gnemul/bsd/" - -static inline char *__emul_prefix(void) -{ - switch (current->personality) { - case PER_BSD: - return ARM_BSD_EMUL; - default: - return NULL; - } -} - -#endif /* __ASMARM_NAMEI_H */ -- cgit v1.2.1 From 6cab48602996cdbcb277375a8107d53e21e8c9b9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Jul 2008 04:23:31 +0100 Subject: [ARM] 5179/1: Replace obsolete IRQT_* and __IRQT_* values with IRQ_TYPE_* IRQT_* and __IRQT_* were obsoleted long ago by patch [3692/1]. Remove them completely. Sed script for the reference: s/__IRQT_RISEDGE/IRQ_TYPE_EDGE_RISING/g s/__IRQT_FALEDGE/IRQ_TYPE_EDGE_FALLING/g s/__IRQT_LOWLVL/IRQ_TYPE_LEVEL_LOW/g s/__IRQT_HIGHLVL/IRQ_TYPE_LEVEL_HIGH/g s/IRQT_RISING/IRQ_TYPE_EDGE_RISING/g s/IRQT_FALLING/IRQ_TYPE_EDGE_FALLING/g s/IRQT_BOTHEDGE/IRQ_TYPE_EDGE_BOTH/g s/IRQT_LOW/IRQ_TYPE_LEVEL_LOW/g s/IRQT_HIGH/IRQ_TYPE_LEVEL_HIGH/g s/IRQT_PROBE/IRQ_TYPE_PROBE/g s/IRQT_NOEDGE/IRQ_TYPE_NONE/g Signed-off-by: Dmitry Baryshkov Signed-off-by: Russell King --- include/asm-arm/arch-pnx4008/irqs.h | 48 ++++++++++++++--------------- include/asm-arm/arch-pxa/idp.h | 10 +++--- include/asm-arm/arch-pxa/pcm990_baseboard.h | 14 ++++----- include/asm-arm/arch-sa1100/ide.h | 2 +- include/asm-arm/irq.h | 17 ---------- 5 files changed, 37 insertions(+), 54 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-pnx4008/irqs.h b/include/asm-arm/arch-pnx4008/irqs.h index 13ec7ed0f501..a25d18f2d87a 100644 --- a/include/asm-arm/arch-pnx4008/irqs.h +++ b/include/asm-arm/arch-pnx4008/irqs.h @@ -135,30 +135,30 @@ #define PNX4008_IRQ_TYPES \ { /*IRQ #'s: */ \ -IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \ -IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \ -IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \ -IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \ -IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \ +IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \ +IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \ +IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \ +IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \ } /* Start Enable Pin Interrupts - table 58 page 66 */ diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h index b6952534a4e1..21aa8ac35c1c 100644 --- a/include/asm-arm/arch-pxa/idp.h +++ b/include/asm-arm/arch-pxa/idp.h @@ -138,18 +138,18 @@ #define TOUCH_PANEL_IRQ IRQ_GPIO(5) #define IDE_IRQ IRQ_GPIO(21) -#define TOUCH_PANEL_IRQ_EDGE IRQT_FALLING +#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING #define ETHERNET_IRQ IRQ_GPIO(4) -#define ETHERNET_IRQ_EDGE IRQT_RISING +#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING -#define IDE_IRQ_EDGE IRQT_RISING +#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCMCIA_S0_CD_VALID IRQ_GPIO(7) -#define PCMCIA_S0_CD_VALID_EDGE IRQT_BOTHEDGE +#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH #define PCMCIA_S1_CD_VALID IRQ_GPIO(8) -#define PCMCIA_S1_CD_VALID_EDGE IRQT_BOTHEDGE +#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH #define PCMCIA_S0_RDYINT IRQ_GPIO(19) #define PCMCIA_S1_RDYINT IRQ_GPIO(22) diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h index b699d0d7bdb2..2e2013179063 100644 --- a/include/asm-arm/arch-pxa/pcm990_baseboard.h +++ b/include/asm-arm/arch-pxa/pcm990_baseboard.h @@ -29,14 +29,14 @@ /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ #define PCM990_CTRL_INT_IRQ_GPIO 9 #define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO) -#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING +#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ #define PCM990_CTRL_BASE 0xea000000 #define PCM990_CTRL_SIZE (1*1024*1024) #define PCM990_CTRL_PWR_IRQ_GPIO 14 #define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO) -#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING +#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING /* visible CPLD (U7) registers */ #define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ @@ -133,7 +133,7 @@ */ #define PCM990_IDE_IRQ_GPIO 13 #define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO) -#define PCM990_IDE_IRQ_EDGE IRQT_RISING +#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ #define PCM990_IDE_PLD_BASE 0xee000000 #define PCM990_IDE_PLD_SIZE (1*1024*1024) @@ -189,11 +189,11 @@ */ #define PCM990_CF_IRQ_GPIO 11 #define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO) -#define PCM990_CF_IRQ_EDGE IRQT_RISING +#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CF_CD_GPIO 12 #define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO) -#define PCM990_CF_CD_EDGE IRQT_RISING +#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING #define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ #define PCM990_CF_PLD_BASE 0xef000000 @@ -259,14 +259,14 @@ */ #define PCM990_AC97_IRQ_GPIO 10 #define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO) -#define PCM990_AC97_IRQ_EDGE IRQT_RISING +#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING /* * MMC phyCORE */ #define PCM990_MMC0_IRQ_GPIO 9 #define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO) -#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING +#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING /* * USB phyCore diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h index b14cbda01dc3..193f6c15f4dd 100644 --- a/include/asm-arm/arch-sa1100/ide.h +++ b/include/asm-arm/arch-sa1100/ide.h @@ -61,7 +61,7 @@ ide_init_default_hwifs(void) /* Enable GPIO as interrupt line */ GPDR &= ~LART_GPIO_IDE; - set_irq_type(LART_IRQ_IDE, IRQT_RISING); + set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING); /* set PCMCIA interface timing */ MECR = 0x00060006; diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h index 1b882a255e35..9cb01907e43b 100644 --- a/include/asm-arm/irq.h +++ b/include/asm-arm/irq.h @@ -19,23 +19,6 @@ #define NO_IRQ ((unsigned int)(-1)) #endif - -/* - * Migration helpers - */ -#define __IRQT_FALEDGE IRQ_TYPE_EDGE_FALLING -#define __IRQT_RISEDGE IRQ_TYPE_EDGE_RISING -#define __IRQT_LOWLVL IRQ_TYPE_LEVEL_LOW -#define __IRQT_HIGHLVL IRQ_TYPE_LEVEL_HIGH - -#define IRQT_NOEDGE (0) -#define IRQT_RISING (__IRQT_RISEDGE) -#define IRQT_FALLING (__IRQT_FALEDGE) -#define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE) -#define IRQT_LOW (__IRQT_LOWLVL) -#define IRQT_HIGH (__IRQT_HIGHLVL) -#define IRQT_PROBE IRQ_TYPE_PROBE - #ifndef __ASSEMBLY__ struct irqaction; extern void migrate_irqs(void); -- cgit v1.2.1 From daf93dd55c48b65ab2f1907e0fc5ef994896c787 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 27 Jul 2008 10:10:58 +0100 Subject: [ARM] fix VIPT/VIVT macro optimisations, add comments cacheflush.h was doing: ... VIVT only stuff ... VIPT only stuff ... VIVT or VIPT stuff which is clearly bogus - we would only ever use the "VIVT or VIPT" case when both VIVT and VIPT are not selected. Fix this. Add comments to each case, including noting the impossibility of correctly detecting the cache type of ARM926 and ARMv6 cores from the cache type register in the "VIVT or VIPT" case. Signed-off-by: Russell King --- include/asm-arm/cacheflush.h | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 03cf1ee977b7..e68a1cbcc852 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, #define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0) #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) - +/* + * VIVT caches only + */ #define cache_is_vivt() 1 #define cache_is_vipt() 0 #define cache_is_vipt_nonaliasing() 0 #define cache_is_vipt_aliasing() 0 #define icache_is_vivt_asid_tagged() 0 -#elif defined(CONFIG_CPU_CACHE_VIPT) - +#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT) +/* + * VIPT caches only + */ #define cache_is_vivt() 0 #define cache_is_vipt() 1 #define cache_is_vipt_nonaliasing() \ @@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, }) #else - +/* + * VIVT or VIPT caches. Note that this is unreliable since ARM926 + * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test. + * There's no way to tell from the CacheType register what type (!) + * the cache is. + */ #define cache_is_vivt() \ ({ \ unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ -- cgit v1.2.1 From 399dee2371787825a1845de87c0cbee7b7c30ad6 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 28 Jul 2008 12:04:06 +0100 Subject: i2c: S3C2410: Pass the I2C bus number via drivers platform data Allow the platform data to specify the bus bumber that the new I2C bus will be given. This is to allow the use of the board registration mechanism to specify the new style of I2C device registration which allows boards to provide a list of attached devices. Note, as discussed on the mailing list, we have dropped backwards compatibility of adding an dynamic bus number as it should not affect most boards to have the bus pinned to 0 if they have either not specified platform data for driver. Any board supplying platform data will automatically have the bus_num field set to 0, and anyone who needs the driver on a different bus number can supply platform data to set bus_num. Signed-off-by: Ben Dooks --- include/asm-arm/plat-s3c/iic.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/plat-s3c/iic.h b/include/asm-arm/plat-s3c/iic.h index 71211c8b5384..d08a1f2863e4 100644 --- a/include/asm-arm/plat-s3c/iic.h +++ b/include/asm-arm/plat-s3c/iic.h @@ -21,6 +21,7 @@ */ struct s3c2410_platform_i2c { + int bus_num; /* bus number to use */ unsigned int flags; unsigned int slave_addr; /* slave address for controller */ unsigned long bus_freq; /* standard bus frequency */ -- cgit v1.2.1