From e18c080fb8695d038f69c26c248f5ecbd9e8aa77 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 31 Jan 2013 14:57:33 +1000 Subject: drm/nouveau/fence/nv84-: put processes to sleep while waiting on fences Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nv84_fence.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nv84_fence.c') diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index c686650584b6..e64e8154a5af 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -47,15 +47,16 @@ nv84_fence_emit(struct nouveau_fence *fence) { struct nouveau_channel *chan = fence->channel; struct nouveau_fifo_chan *fifo = (void *)chan->object; - int ret = RING_SPACE(chan, 7); + int ret = RING_SPACE(chan, 8); if (ret == 0) { BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); OUT_RING (chan, NvSema); - BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); + BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); OUT_RING (chan, upper_32_bits(fifo->chid * 16)); OUT_RING (chan, lower_32_bits(fifo->chid * 16)); OUT_RING (chan, fence->sequence); OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); + OUT_RING (chan, 0x00000000); FIRE_RING (chan); } return ret; @@ -174,6 +175,9 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.sync = nv84_fence_sync; priv->base.read = nv84_fence_read; + init_waitqueue_head(&priv->base.waiting); + priv->base.uevent = true; + ret = nouveau_gpuobj_new(drm->device, NULL, chan * 16, 0x1000, 0, &priv->mem); if (ret) -- cgit v1.2.1