From f79abb627f033c85a6088231f20c85bc4a9bd757 Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Tue, 18 Mar 2008 18:45:00 -0700 Subject: fsldma: Fix the DMA halt when using DMA_INTERRUPT async_tx transfer. The DMA_INTERRUPT async_tx is a NULL transfer, thus the BCR(count register) is 0. When the transfer started with a byte count of zero, the DMA controller will triger a PE(programming error) event and halt, not a normal interrupt. I add special codes for PE event and DMA_INTERRUPT async_tx testing. Signed-off-by: Zhang Wei Signed-off-by: Andrew Morton Signed-off-by: Dan Williams --- drivers/dma/fsldma.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/dma/fsldma.h') diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index ba78c42121ba..fddd6aee2a63 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -40,6 +40,7 @@ #define FSL_DMA_MR_EOTIE 0x00000080 #define FSL_DMA_SR_CH 0x00000020 +#define FSL_DMA_SR_PE 0x00000010 #define FSL_DMA_SR_CB 0x00000004 #define FSL_DMA_SR_TE 0x00000080 #define FSL_DMA_SR_EOSI 0x00000002 -- cgit v1.2.1