From aefc7c7512455c26574ae7118429920dc3de60ae Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Mon, 9 Feb 2015 21:12:22 +0800 Subject: ARM: rockchip: decrease the wait time for resume The register-default delay time for wait the 24MHz OSC stabilization as well as PMU stabilization is 750ms, let's decrease them to a still safe 30ms. Signed-off-by: Chris Zhong Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/pm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-rockchip/pm.c') diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index 50cb781aaa36..a3ab3979923c 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -209,6 +209,9 @@ static int rk3288_suspend_init(struct device_node *np) memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume, rk3288_bootram_sz); + regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH); + regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH); + return 0; } -- cgit v1.2.1 From a0307d186f5015ee3d77e209e5c06190cbf02478 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Mon, 9 Feb 2015 21:12:23 +0800 Subject: ARM: rockchip: disable watchdog during suspend The watchdog clock should be disable in dw_wdt_suspend, but we set a dummy clock to watchdog for rk3288. So the watchdog will continue to work during suspend. And we switch the system clock to 32khz from 24Mhz, during suspend, so the watchdog timer over count will increase to 755 times, about 12.5 hours, the original value is 60 seconds. So watchdog will reset the system over a night, but voltage are all incorrect, then it hang on reset. Signed-off-by: Chris Zhong Signed-off-by: Daniel Kurtz Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/pm.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-rockchip/pm.c') diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index a3ab3979923c..b07d88602073 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -75,9 +75,13 @@ static void rk3288_slp_mode_set(int level) regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, &rk3288_pmu_pwr_mode_con); - /* set bit 8 so that system will resume to FAST_BOOT_ADDR */ + /* + * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR + * PCLK_WDT_GATE - disable WDT during suspend. + */ regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, - SGRF_FAST_BOOT_EN | SGRF_FAST_BOOT_EN_WRITE); + SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN + | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE); /* booting address of resuming system is from this register value */ regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, @@ -122,7 +126,8 @@ static void rk3288_slp_mode_set_resume(void) rk3288_pmu_pwr_mode_con); regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, - rk3288_sgrf_soc_con0 | SGRF_FAST_BOOT_EN_WRITE); + rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE + | SGRF_FAST_BOOT_EN_WRITE); } static int rockchip_lpmode_enter(unsigned long arg) -- cgit v1.2.1