From efd09165aa554f84a42565d5ae6a1af58b06a97a Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Mon, 13 Feb 2012 14:58:30 +0800 Subject: ARM: at91: pm select memory controler at runtime Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD [nicolas.ferre@atmel.com: add cpuidle modification] Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm.h | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'arch/arm/mach-at91/pm.h') diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 89f56f3a802e..1b4865e7571d 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -12,7 +12,6 @@ #define __ARCH_ARM_MACH_AT91_PM #include -#ifdef CONFIG_ARCH_AT91RM9200 #include /* @@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void) "r" (lpr)); } -#define at91_standby at91rm9200_standby - -#elif defined(CONFIG_ARCH_AT91SAM9G45) - /* We manage both DDRAM/SDRAM controllers, we need more than one value to * remember. */ @@ -75,10 +70,6 @@ static inline void at91sam9g45_standby(void) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } -#define at91_standby at91sam9g45_standby - -#else - #ifdef CONFIG_ARCH_AT91SAM9263 /* * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; @@ -102,8 +93,4 @@ static inline void at91sam9_standby(void) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr); } -#define at91_standby at91sam9_standby - -#endif - #endif -- cgit v1.2.1