From 05118a8e1435c2706d63e8411390d6e16e13e17c Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 06:49:53 +0900 Subject: ARM: dts: Add missing op_mode property to PMIC on Arndale Though the default value is 1, add it explicitly to avoid unnecessary boot warnings and for consistency. Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-arndale.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 684527087aa4..bbfb23f942e1 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -302,11 +302,13 @@ buck7_reg: BUCK7 { regulator-name = "PVDD_BUCK7"; regulator-always-on; + op_mode = <1>; }; buck8_reg: BUCK8 { regulator-name = "PVDD_BUCK8"; regulator-always-on; + op_mode = <1>; }; buck9_reg: BUCK9 { -- cgit v1.2.1 From 0da805639fac5bf729b4880ee14c4abff2c202d0 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 06:54:34 +0900 Subject: ARM: dts: Add missing frequency property to exynos5250 Added missing clock frequency property to CPU node to avoid boot time warnings. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 9db5047812f3..d871e6241d8a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -60,11 +60,13 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + clock-frequency = <1700000000>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + clock-frequency = <1700000000>; }; }; -- cgit v1.2.1 From 505d41ecbc650afd1724403754694e662e1ba0da Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 06:58:37 +0900 Subject: ARM: dts: Fix a typo in exynos5420-pinctrl.dtsi Fixed samaung -> samsung in property name. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index e695aba5f73c..e62c8eb57438 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -64,7 +64,7 @@ samsung,pins = "gpx0-7"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samaung,pin-drv = <0>; + samsung,pin-drv = <0>; }; }; -- cgit v1.2.1 From 67ddd05382d98a106b75dba47f7550456ab5f832 Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Thu, 12 Dec 2013 07:45:07 +0900 Subject: ARM: dts: Update display clock frequency for Origen-4210 As per the timing information for supported panel, the value should be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate. Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152 Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683 Target pixel clock rate for refresh rate @60 Hz = 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz Signed-off-by: Tushar Behera Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-origen.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 1a12fb23767c..2aa13cb3bbed 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -313,7 +313,7 @@ display-timings { native-mode = <&timing0>; timing0: timing { - clock-frequency = <50000>; + clock-frequency = <47500000>; hactive = <1024>; vactive = <600>; hfront-porch = <64>; -- cgit v1.2.1 From 236940d2c951a84735fdd7b958b5159eaf501784 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 07:45:12 +0900 Subject: ARM: dts: Update display clock frequency for Origen-4412 As per the timing information for supported panel, the value should be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate. Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152 Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683 Target pixel clock rate for refresh rate @60 Hz = 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-origen.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index d65984c440f6..95201559c3ad 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -159,7 +159,7 @@ display-timings { native-mode = <&timing0>; timing0: timing { - clock-frequency = <50000>; + clock-frequency = <47500000>; hactive = <1024>; vactive = <600>; hfront-porch = <64>; -- cgit v1.2.1 From c63965b3b6936f5268a4ade24c507fe297cb236c Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Sat, 21 Dec 2013 06:08:15 +0900 Subject: ARM: dts: Add the missing "\" key in non-US keyboards for exynos5250-snow When the exynos5250 device tree was sent upstream the keyboard mapping was missing the 2nd instance of the "\" key. There are two copies of the "\" because it simply has a different row and column on US and non-US keyboards. For more details, see the previous patch in this series: (mkbp: Fix problems with backslash). Signed-off-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-snow.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index fd711e245e8d..28fe2e29dde0 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -130,6 +130,7 @@ 0x04060024 /* J */ 0x04080027 /* ; */ 0x04090026 /* L */ + 0x040a002b /* \ */ 0x040b001c /* ENTER */ 0x0501002c /* Z */ -- cgit v1.2.1 From a98e3190fc7dbb6157ef51ce8d92a36b06d282bb Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Sat, 21 Dec 2013 06:08:20 +0900 Subject: ARM: dts: Fix exynos5250-snow's search key to be L_META The device tree sent upstream for exynos5250-snow encoded the search key as CAPSLK. However in all ChromeOS kernels it is L_META. One can certainly have long debates about which it ought to be, but I'm proposing setting it to L_META because: * That's how _all_ ChromeOS kernels do it and will do it. * There is no L_META key on the board, so it's nice to have. * For those people who really want it to be caps lock, they can use xmodmap or somesuch. Signed-off-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-snow.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 28fe2e29dde0..c65f52a6dcea 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -85,7 +85,7 @@ keypad,num-rows = <8>; keypad,num-columns = <13>; google,needs-ghost-filter; - linux,keymap = <0x0001003a /* CAPSLK */ + linux,keymap = <0x0001007d /* L_META */ 0x0002003b /* F1 */ 0x00030030 /* B */ 0x00040044 /* F10 */ -- cgit v1.2.1 From 14cd57142c29a6b9dcd32f2146972295f2ff58ab Mon Sep 17 00:00:00 2001 From: Seungwon Jeon Date: Sat, 21 Dec 2013 05:43:40 +0900 Subject: ARM: dts: add clock provider for mshc node for Exynos4412 SOC Clock lookup information is required as driver can manipulate clock rate properly. Signed-off-by: Seungwon Jeon Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index e743e677a9e2..8cb1469c7d7f 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -67,5 +67,7 @@ interrupts = <0 77 0>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clock 301>, <&clock 149>; + clock-name = "biu", "ciu"; }; }; -- cgit v1.2.1 From 56d52bfb9ce0dfed7ee3059a8111534bffa53274 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Sat, 21 Dec 2013 07:37:30 +0900 Subject: ARM: dts: Fix definition of MSHC device tree nodes for exynos4x12 All SoCs from Exynos4x12 series contain the MSHC block, so its node can be located in exynos4x12.dtsi. In addition, missing clock specifiers are added, generic SoC attributes are moved from board dts files to common dtsi file of SoC family and the node is renamed to a more generic name to follow node naming recommendations. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-odroidx.dts | 5 +---- arch/arm/boot/dts/exynos4412-origen.dts | 5 +---- arch/arm/boot/dts/exynos4412.dtsi | 9 --------- arch/arm/boot/dts/exynos4x12.dtsi | 13 +++++++++++++ 4 files changed, 15 insertions(+), 17 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 46c678ee119c..8aad5f72ced7 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -38,9 +38,7 @@ }; }; - mshc@12550000 { - #address-cells = <1>; - #size-cells = <0>; + mmc@12550000 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; vmmc-supply = <&ldo20_reg &buck8_reg>; @@ -49,7 +47,6 @@ num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 95201559c3ad..6bc053924e9e 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -122,9 +122,7 @@ status = "okay"; }; - mshc@12550000 { - #address-cells = <1>; - #size-cells = <0>; + mmc@12550000 { pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; status = "okay"; @@ -132,7 +130,6 @@ num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 8cb1469c7d7f..85812bd95a86 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -61,13 +61,4 @@ }; }; - mshc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock 301>, <&clock 149>; - clock-name = "biu", "ciu"; - }; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index ad531fe6ab95..1917c829e64e 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -28,6 +28,7 @@ pinctrl3 = &pinctrl_3; fimc-lite0 = &fimc_lite_0; fimc-lite1 = &fimc_lite_1; + mshc0 = &mshc_0; }; pd_isp: isp-power-domain@10023CA0 { @@ -176,4 +177,16 @@ }; }; }; + + mshc_0: mmc@12550000 { + compatible = "samsung,exynos4412-dw-mshc"; + reg = <0x12550000 0x1000>; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <0x80>; + clocks = <&clock 301>, <&clock 149>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; }; -- cgit v1.2.1 From ca7c11fc8df0657ddeffc1cd98428abd739e1e10 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Sat, 21 Dec 2013 07:38:19 +0900 Subject: ARM: dts: Use MSHC controller for eMMC memory for exynos4412-trats2 This patch removes device tree node of SDHCI0 controller and replaces it with MSHC to enable support MMC 4.4 and improve performance of eMMC memory. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4412-trats2.dts | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index fb7b9ae5f399..890ad275cb85 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -442,13 +442,25 @@ }; }; - sdhci@12510000 { - bus-width = <8>; + mmc@12550000 { + num-slots = <1>; + supports-highspeed; + broken-cd; non-removable; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; - pinctrl-names = "default"; + card-detect-delay = <200>; vmmc-supply = <&vemmc_reg>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; status = "okay"; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; }; serial@13800000 { -- cgit v1.2.1