From b1342b2581181e4ec54b43edc5c4a18cef9b6a1d Mon Sep 17 00:00:00 2001 From: johnhcwang Date: Thu, 21 Jul 2016 06:01:10 -0500 Subject: arm/aspeed: Fix the debounce setting on power button PCLK divider selection is decided by SCU08[25:23] and the value is 011b on Barreleye. That means PCLK should be H-PLL/8=384MHz/8=48MHz, but the current debounce timer value was computed by 24MHz. So the correct value should be 20ms*48000000/1000=EA600h Signed-off-by: John Wang Signed-off-by: Joel Stanley --- arch/arm/mach-aspeed/aspeed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c index 11d8a61b6ad6..fadbbb666e1d 100755 --- a/arch/arm/mach-aspeed/aspeed.c +++ b/arch/arm/mach-aspeed/aspeed.c @@ -159,9 +159,9 @@ static void __init do_barreleye_setup(void) writel(0x00000001, AST_IO(AST_BASE_GPIO | 0x48)); writel(0x00000001, AST_IO(AST_BASE_GPIO | 0x4C)); - /* Set debounce timer to 480000 cycles, with a pclk of 24MHz, + /* Set debounce timer to 480000 cycles, with a pclk of 48MHz, * corresponds to 20 ms. This time was found by experimentation */ - writel(0x00075300, AST_IO(AST_BASE_GPIO | 0x58)); + writel(0x000EA600, AST_IO(AST_BASE_GPIO | 0x58)); } static void __init do_palmetto_setup(void) -- cgit v1.2.1