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* mtd: mtdram: add missing 'const'Brian Norris2014-01-201-1/+1
| | | | | | | mtdram_init_device() wasn't updated along with mtd_partition.name. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org>
* mtd: nand: add Intel manufacturer IDHuang Shijie2014-01-201-0/+1
| | | | | | | | | Add the Intel manufacturer Id. Tested with Intel JS29F32G08ACMD1(4096 + 224) which is ONFI 2.0 compliant nand. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add SanDisk manufacturer IDHuang Shijie2014-01-201-0/+1
| | | | | | | | Add the manufactor ID for SanDisk. Make preparation for SanDisk SDTNRGAMA-008G. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: don't use {read,write}_buf for 8-bit transfersUwe Kleine-König2014-01-141-0/+3
| | | | | | | | | | | | | | | | | | According to the Open NAND Flash Interface Specification (ONFI) Revision 3.1 "Parameters are always transferred on the lower 8-bits of the data bus." for the Get Features and Set Features commands. So using read_buf and write_buf is wrong for 16-bit wide nand chips as they use I/O[15:0]. The Get Features command is easily fixed using 4 times the read_byte callback. For Set Features implement a new overwritable callback "write_byte". Still I expect the default to work just fine for all controllers and making it overwriteable was just done for symmetry. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> [Brian: fixed warning] Tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: use __packed shorthandBrian Norris2014-01-131-1/+1
| | | | | | | | To be consistent with the rest of include/linux/mtd/nand.h, we should use the __packed shorthand instead of __attribute__((packed)). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: support Micron READ RETRYBrian Norris2014-01-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Micron provides READ RETRY support via the ONFI vendor-specific parameter block (to indicate how many read-retry modes are available) and the ONFI {GET,SET}_FEATURES commands with a vendor-specific feature address (to support reading/switching the current read-retry mode). The recommended sequence is as follows: 1. Perform PAGE_READ operation 2. If no ECC error, we are done 3. Run SET_FEATURES with feature address 89h, mode 1 4. Retry PAGE_READ operation 5. If ECC error and there are remaining supported modes, increment the mode and return to step 3. Otherwise, this is a true ECC error. 6. Run SET_FEATURES with feature address 89h, mode 0, to return to the default state. This patch implements the chip->setup_read_retry() callback for Micron and fills in the chip->read_retries. Tested on Micron MT29F32G08CBADA, which supports 8 read-retry modes. The Micron vendor-specific table was checked against the datasheets for the following Micron NAND: Needs retry Cell-type Part number Vendor revision Byte 180 ----------- --------- ---------------- --------------- ------------ No SLC MT29F16G08ABABA 1 Reserved (0) No MLC MT29F32G08CBABA 1 Reserved (0) No SLC MT29F1G08AACWP 1 0 Yes MLC MT29F32G08CBADA 1 08h Yes MLC MT29F64G08CBABA 2 08h Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: add generic READ RETRY supportBrian Norris2014-01-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modern MLC (and even SLC?) NAND can experience a large number of bitflips (beyond the recommended correctability capacity) due to drifts in the voltage threshold (Vt). These bitflips can cause ECC errors to occur well within the expected lifetime of the flash. To account for this, some manufacturers provide a mechanism for shifting the Vt threshold after a corrupted read. The generic pattern seems to be that a particular flash has N read retry modes (where N = 0, traditionally), and after an ECC failure, the host should reconfigure the flash to use the next available mode, then retry the read operation. This process repeats until all bitfips can be corrected or until the host has tried all available retry modes. This patch adds the infrastructure support for a vendor-specific/flash-specific callback, used for setting the read-retry mode (i.e., voltage threshold). For now, this patch always returns the flash to mode 0 (the default mode) after a successful read-retry, according to the flowchart found in Micron's datasheets. This may need to change in the future if it is determined that eventually, mode 0 is insufficient for the majority of the flash cells (and so for performance reasons, we should leave the flash in mode 1, 2, etc.). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com>
* mtd: nand: add ONFI vendor block for MicronBrian Norris2014-01-131-1/+22
| | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com>
* mtd: make register_mtd_parser return voidAxel Lin2014-01-031-1/+1
| | | | | | | register_mtd_parser never fails; hence make it return void. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: make deregister_mtd_parser return voidAxel Lin2014-01-031-1/+1
| | | | | | | deregister_mtd_parser never fails; hence make it return void. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: fix misspelling in ONFI parameter field nameBrian Norris2014-01-031-1/+1
| | | | | | | | s/strenght/strength/ This field isn't used anywhere, so this rename is safe. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: make mtd_partition.name constGeert Uytterhoeven2014-01-031-2/+2
| | | | | | | This allows to drop a few casts. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand_bbt: kill NAND_BBT_SCANALLPAGESBrian Norris2013-11-061-2/+0
| | | | | | | | | Now that the last user of NAND_BBT_SCANALLPAGES has been removed, let's kill this peculiar BBT feature flag. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
* mtd: map: fixed bug in 64-bit systemsWang Haitao2013-11-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware: CPU: XLP832,the 64-bit OS NOR Flash:S29GL128S 128M Software: Kernel:2.6.32.41 Filesystem:JFFS2 When writing files, errors appear: Write len 182 but return retlen 180 Write of 182 bytes at 0x072c815c failed. returned -5, retlen 180 Write len 186 but return retlen 184 Write of 186 bytes at 0x072caff4 failed. returned -5, retlen 184 These errors exist only in 64-bit systems,not in 32-bit systems. After analysis, we found that the left shift operation is wrong in map_word_load_partial. For instance: unsigned char buf[3] ={0x9e,0x3a,0xea}; map_bankwidth(map) is 4; for (i=0; i < 3; i++) { int bitpos; bitpos = (map_bankwidth(map)-1-i)*8; orig.x[0] &= ~(0xff << bitpos); orig.x[0] |= buf[i] << bitpos; } The value of orig.x[0] is expected to be 0x9e3aeaff, but in this situation(64-bit System) we'll get the wrong value of 0xffffffff9e3aeaff due to the 64-bit sign extension: buf[i] is defined as "unsigned char" and the left-shift operation will convert it to the type of "signed int", so when left-shift buf[i] by 24 bits, the final result will get the wrong value: 0xffffffff9e3aeaff. If the left-shift bits are less than 24, then sign extension will not occur. Whereas the bankwidth of the nor flash we used is 4, therefore this BUG emerges. Signed-off-by: Pang Xunlei <pang.xunlei@zte.com.cn> Signed-off-by: Zhang Yi <zhang.yi20@zte.com.cn> Signed-off-by: Lu Zhongjun <lu.zhongjun@zte.com.cn> Cc: <stable@vger.kernel.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: Move major number definitions to major.hEzequiel Garcia2013-11-061-3/+0
| | | | | | | | | This patch moves the char and block major number definitions to major.h to be with the rest of the major numbers. While doing this, include major.h in the files that need it. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add a helper to detect the nand typeHuang Shijie2013-10-271-0/+5
| | | | | | | | | | | This helper detects that whether the mtd's type is nand type. Now, it's clear that the MTD_NANDFLASH stands for SLC nand only. So use the mtd_type_is_nand() to replace the old check method to do the nand type (include the SLC and MLC) check. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: rename the cellinfo to bits_per_cellHuang Shijie2013-10-271-3/+4
| | | | | | | | | | | | | | | | | | | The @cellinfo fields contains unused information, such as write caching, internal chip numbering, etc. But we only use it to check the SLC or MLC. This patch tries to make it more clear and simple, renames the @cellinfo to @bits_per_cell. In order to avoiding the bisect issue, this patch also does the following changes: (0) add a macro NAND_CI_CELLTYPE_SHIFT to avoid the hardcode. (1) add a helper to parse out the cell type : nand_get_bits_per_cell() (2) parse out the cell type for extended-ID chips and the full-id nand chips. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: add a helper to check the SLC/MLC nand chipHuang Shijie2013-10-271-0/+9
| | | | | | | | Add a helper to check if a nand chip is SLC or MLC. This helper makes the code more readable. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: nand: remove obsolete 'ecclayout' fieldBrian Norris2013-10-271-2/+0
| | | | | | This field is never used, except to print it out. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: add a new ecc_step_size field to mtd_info{}Huang Shijie2013-08-301-0/+3
| | | | | | | | | | | | | | | | | | | In order to implement the NAND boot for some Freescale's chips, such as imx23/imx28/imx50/imx6, we use a tool (called kobs-ng) to burn the uboot and some metadata to nand chip. And the ROM code will use the metadata to configrate the BCH, and to find the uboot. The ECC information(ecc step size, ecc strength) which is used to configrure the BCH is part of the metadata. The kobs-ng can get the ecc strength from the sys node /sys/*/ecc_strength now. But it can not get the ecc step size. This patch adds a new field to store the ecc step size in mtd_info{}, and it makes preparation for the next patches. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add ECC info for nand_flash_dev{}Huang Shijie2013-08-301-0/+15
| | | | | | | | | | | | | | | Add an instance of an anonymous struct to store the ECC info for full id nand chips. @ecc.strength_ds: ECC correctability from the datasheet. @ecc.step_ds: ECC size required by the @ecc.strength_ds, These two fields are all from the datasheet. Also add the necessary macros to make the code simple and clean. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add a helper to get the supported features for ONFI nandHuang Shijie2013-08-301-0/+10
| | | | | | | | | | add a helper to get the supported features for ONFI nand. Also add the neccessary macros. Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add data structures for Extended Parameter PageHuang Shijie2013-08-301-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page to store the ECC info. The onfi spec tells us that if the nand chip's recommended ECC codeword size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then read the Extended ECC information that is part of the extended parameter page to retrieve the ECC requirements for this device. This patch adds [1] the neccessary fields for nand_onfi_params{}, [2] and adds the onfi_ext_ecc_info{} for Extended ECC information, [3] adds onfi_ext_section{} for extended sections, [4] and adds onfi_ext_param_page{} for the Extended Parameter Page. Acked-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> [Brian: amended for checkpatch.pl] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add datasheet's ECC information to nand_chip{}Huang Shijie2013-08-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1.) Why add the ECC information to the nand_chip{} ? Each nand chip has its requirement for the ECC correctability, such as "4bit ECC for each 512Byte" or "40bit ECC for each 1024Byte". This ECC info is very important to the nand controller, such as gpmi. Take the Micron MT29F64G08CBABA for example, its geometry is 8KiB page size, 744 bytes oob size and it requires 40bit ECC per 1KiB. If we do not provide the ECC info to the gpmi nand driver, it has to calculate the ECC correctability itself. The gpmi driver will gets the 56bit ECC for per 1KiB which is beyond its BCH's 40bit ecc capibility. The gpmi will quits in this case. But in actually, the gpmi can supports this nand chip if it can get the right ECC info. 2.) about the new fields. The @ecc_strength_ds stands for the ecc bits needed within the @ecc_step_ds. The two fields should be set from the nand chip's datasheets. For example: "4bit ECC for each 512Byte" could be: @ecc_strength_ds = 4, @ecc_step_ds = 512. "40bit ECC for each 1024Byte" could be: @ecc_strength_ds = 40, @ecc_step_ds = 1024. 3.) Why do not re-use the @strength and @size in the nand_ecc_ctrl{}? The @strength and @size in nand_ecc_ctrl{} is used by the nand controller driver, while the @ecc_strength_ds and @ecc_step_ds are get from the datasheet. Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: remove NAND_BBT_SCANEMPTYBrian Norris2013-08-301-2/+0
| | | | | | | | | | | | | | | | | | NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its single remaining user. NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway, omap2 doesn't scan the chip for bad blocks (courtesy of NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant. This patch drops the NAND_BBT_SCANEMPTY option. [1] http://lists.infradead.org/pipermail/linux-mtd/2012-July/042902.html Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Ivan Djelic <ivan.djelic@parrot.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: hide in-memory BBT implementation detailsBrian Norris2013-08-301-1/+1
| | | | | | | | | | | | | | | | nand_base.c shouldn't have to know the implementation details of nand_bbt's in-memory BBT. Specifically, nand_base shouldn't perform the bit masking and shifting to isolate a BBT entry. Instead, just move some of the BBT code into a new nand_markbad_bbt() interface. This interface allows external users (i.e., nand_base) to mark a single block as bad in the BBT. Then nand_bbt will take care of modifying the in-memory BBT and updating the flash-based BBT (if applicable). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand_base: Only use GET/SET FEATURES command on chips that support them.David Mosberger2013-08-051-0/+3
| | | | | | | | Spansion's S34MLx chips support ONFI but not the GET/SET FEATURES calls. Signed-off-by: David Mosberger <dmosberger@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: fsmc: update of OF supportMian Yousaf Kaukab2013-08-051-0/+1
| | | | | | | | | | | Add nand bank selection and timings to the device tree bindings. Signed-off-by: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> [Added some documentation] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: increase max OOB size to 744Huang Shijie2013-08-051-1/+1
| | | | | | | | | The oob size of Micron's MT29F64G08CBABAWP is 744 bytes. So increase the NAND_MAX_OOBSIZE to 744. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: reword nand_chip bad block interface commentsBrian Norris2013-08-051-2/+2
| | | | | | | | | | | | | | | This remedies a few problems: (1) The use of "the" vs. "a" is a little confusing, IMO. (2) nand_chip.block_bad is used exclusively for checking the OOB bad block markers of a NAND. Any BBT functionality is handled in nand_bbt.c, so this description should differentiate itself from nand_bbt.c. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* Merge tag 'for-linus-20130509' of git://git.infradead.org/linux-mtdLinus Torvalds2013-05-094-67/+68
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD update from David Woodhouse: - Lots of cleanups from Artem, including deletion of some obsolete drivers - Support partitions larger than 4GiB in device tree - Support for new SPI chips * tag 'for-linus-20130509' of git://git.infradead.org/linux-mtd: (83 commits) mtd: omap2: Use module_platform_driver() mtd: bf5xx_nand: Use module_platform_driver() mtd: denali_dt: Remove redundant use of of_match_ptr mtd: denali_dt: Change return value to fix smatch warning mtd: denali_dt: Use module_platform_driver() mtd: denali_dt: Fix incorrect error check mtd: nand: subpage write support for hardware based ECC schemes mtd: omap2: use msecs_to_jiffies() mtd: nand_ids: use size macros mtd: nand_ids: improve LEGACY_ID_NAND macro a bit mtd: add 4 Toshiba nand chips for the full-id case mtd: add the support to parse out the full-id nand type mtd: add new fields to nand_flash_dev{} mtd: sh_flctl: Use of_match_ptr() macro mtd: gpio: Use of_match_ptr() macro mtd: gpio: Use devm_kzalloc() mtd: davinci_nand: Use of_match_ptr() mtd: dataflash: Use of_match_ptr() macro mtd: remove h720x flash support mtd: onenand: remove OneNAND simulator ...
| * mtd: nand: subpage write support for hardware based ECC schemesGupta, Pekon2013-04-051-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for subpage (partial-page) writes when using hardware based ECC schemes. Advantages: (1) reduces storage overhead when using file-systems like UBIFS, which store LEB header at page-size granularity. (2) allows independent subpage writes, thereby increasing NAND storage efficiency for non-page aligned data. + updated cafe_nand and lpc32xx_mlc NAND drivers for change in chip->write_page interface. Signed-off-by: Gupta, Pekon <pekon@ti.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand_ids: improve LEGACY_ID_NAND macro a bitArtem Bityutskiy2013-04-051-5/+4
| | | | | | | | | | | | | | | | | | Notice that all the flashes belonging to the "legacy ID" class have 512 bytes NAND page. This means we may simplify the 'LEGACY_ID_NAND()' macro as well as the NAND ID table a little. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: add new fields to nand_flash_dev{}Huang Shijie2013-04-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As time goes on, we begin to meet the situation that we can not get enough information from some nand chips's id data. Take some Toshiba's nand chips for example. I have 4 Toshiba's nand chips in my hand: TC58NVG2S0F, TC58NVG3S0F, TC58NVG5D2, TC58NVG6D2 When we read these chips' datasheets, we will get the geometry of these chips: TC58NVG2S0F : 4096 + 224 TC58NVG3S0F : 4096 + 232 TC58NVG5D2 : 8192 + 640 TC58NVG6D2 : 8192 + 640 But we can not parse out the correct oob size for these chips from the id data. This patch adds some new fields to the nand_flash_dev{}: @id_len: the valid length of the id data. See the comments in nand_id_has_period() @oobsize: the oob size. Signed-off-by: Huang Shijie <b32955@freescale.com> Reviewed-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: introduce a macro for max NAND ID sequence lengthArtem Bityutskiy2013-04-051-1/+4
| | | | | | | | | | | | | | | | | | Introduce a helpful macro for the maximum NAND ID sequence length instead of using the "8" magic number. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: use more reasonable integer typesArtem Bityutskiy2013-04-051-5/+5
| | | | | | | | | | | | | | | | | | | | | | Use 'unsigned int' instead of 'unsigned long' in the NAND chip description data structure, because 32-bits is more than enough for our purposes. We do not need 64-bits, which is what we end up on 64-bit architectures. We declare many instances of this data structure, so this should help saving some amount of memory. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: physmap: add const qualifiersArtem Bityutskiy2013-04-051-1/+1
| | | | | | | | | | | | | | Be a bit stricter and add few more 'const' qualifiers. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: plat-ram: add const quilifiersArtem Bityutskiy2013-04-051-2/+2
| | | | | | | | | | | | | | Be a bit stricter and add few more 'const' qualifiers. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: add 'const' qualifier to a couple of register functionsArtem Bityutskiy2013-04-051-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'mtd_device_parse_register()' and 'parse_mtd_partitions()' functions accept a an array of character pointers. These functions modify neither the pointers nor the characters they point to. The characters are actually names of the MTD parsers. At the moment, the argument type is 'const char **', which means that only the names of the parsers are constant. Let's turn the argument type into 'const char * const *', which means that both names and the pointers which point to them are constant. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: provision full ID supportArtem Bityutskiy2013-04-051-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up until now we identified NAND chips by the 'device ID' part of the full chip ID array, which is the second full ID array byte. However, the newest flashes use the same device ID for chips with identical page and eraseblock sizes, but different OOB sizes. And unfortunately, it is not clear if there is a "standard" way to fetch the OOB size from chip's full ID array. Here is an example: Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08 Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08 The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page and eraseblock sizes, but with 232 bytes OOB. This means that we have to store full ID in our NAND flashes table in order to distinguish between these 2. This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and it makes it to be a part of anonymous union, where the second member is a structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that 'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same RAM address as 'id[1]'. The only motivation for the union is an assumption that 'type->dev_id' is more readable than 'type->id[1]'. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand_ids: introduce helper macrosArtem Bityutskiy2013-04-051-0/+24
| | | | | | | | | | | | | | | | | | | | Introduce helper macros for defining NAND chips. These macros do not really add much value in the current code-base. However, we are going to add full ID support which adds some more complexity to the table, and helper macros become useful for readability. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: rename the id field of 'struct nand_flash_dev'Artem Bityutskiy2013-04-051-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | The 'id' is a bit confusing name because NAND IDs are multi-byte. Re-name it to 'dev_id' to make it clear that this is the "device ID" part (the second byte). While on it, clean-up the commentary for 'struct nand_flash_dev'. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: use NAND_HAS_CACHEPROGArtem Bityutskiy2013-04-051-1/+1
| | | | | | | | | | | | | | | | We have this unused macro, let's use it and justify its existence. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: remove NAND_COPYBACK macroArtem Bityutskiy2013-04-051-4/+1
| | | | | | | | | | | | | | | | It is unused. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: remove NAND_NO_PADDING macroArtem Bityutskiy2013-04-051-5/+1
| | | | | | | | | | | | | | | | It is not used anywhere. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: remove a bunch of unused commandsArtem Bityutskiy2013-04-051-20/+0
| | | | | | | | | | | | Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * mtd: nand: remove AG-AND supportArtem Bityutskiy2013-04-051-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have only one AG-AND driver and it was not touched since 2005. It looks like AG-AND was not really make it to mass-production and can be considered a dead technology. Along with the AG-AND support, this patch removes the BBT_AUTO_REFRESH feature, because the only user of this feature is AG-AND. And even though it is implemented as a generic feature, I prefer to remove it because NAND flashes do not really need it in this form. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* | mtd_blktrans_ops->release() should return voidAl Viro2013-05-051-1/+1
|/ | | | | | | Both existing instances always return 0 and even if they didn't, the value would be lost on the way out. Just don't bother... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* mtd: nand: reintroduce NAND_NO_READRDY as NAND_NEED_READRDYBrian Norris2013-03-141-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | This partially reverts commit 1696e6bc2ae83734e64e206ac99766ea19e9a14e ("mtd: nand: kill NAND_NO_READRDY"). In that patch I overlooked a few things. The original documentation for NAND_NO_READRDY included "True for all large page devices, as they do not support autoincrement." I was conflating "not support autoincrement" with the NAND_NO_AUTOINCR option, which was in fact doing nothing. So, when I dropped NAND_NO_AUTOINCR, I concluded that I then could harmlessly drop NAND_NO_READRDY. But of course the fact the NAND_NO_AUTOINCR was doing nothing didn't mean NAND_NO_READRDY was doing nothing... So, NAND_NO_READRDY is re-introduced as NAND_NEED_READRDY and applied only to those few remaining small-page NAND which needed it in the first place. Cc: stable@kernel.org [3.5+] Reported-by: Alexander Shiyan <shc_work@mail.ru> Tested-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: map: BUG() in non handled casesDmitry Eremin-Solenikov2013-02-221-2/+6
| | | | | | | | | | | Several map-related functions look like a serie of ifs, checking widths of map. Those functions do not have any handling for default case. Instead of fiddling with uninitialized_var in those functions, let's just add a (correct) BUG() to the default case on those maps. This will also allow us to catch potential errors in maps setup in future. Signed-off-by: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
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