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* mmc: sdhci: Remove the sdhci exported header fileUlf Hansson2015-03-231-220/+0
| | | | | | | | | | Since there no users of the struct sdhci_host, but the shdci host drivers themselves, let's move the definition of it to the local sdhci header. The exported sdhci header then becomes empty, so let's remove it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: add quirk for ACMD23 brokenScott Branden2015-03-231-0/+2
| | | | | | | | | | | | Add quirk to handle broken auto-CMD23. Some controllers do not respond after the first auto-CMD23 is issued. This allows CMD23 to still work (mandatory for the faster UHS-I mode) rather than disabling CMD23 entirely via SDHCI_QUIRK2_HOST_NO_CMD23. Signed-off by: Corneliu Doban <cdoban@broadcom.com> Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: add a quirk for single block transactionsVincent Yang2015-01-201-0/+2
| | | | | | | | | | This patch defines a quirk to disable the block count for single block transactions. It is a preparation and will be used by Fujitsu SDHCI controller f_sdh30 driver. Signed-off-by: Vincent Yang <Vincent.Yang@tw.fujitsu.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: add a quirk for tuning work aroundVincent Yang2015-01-201-0/+2
| | | | | | | | | | | | This patch defines a quirk for tuning work around for some sdhci host controller. It sets both SDHCI_CTRL_EXEC_TUNING and SDHCI_CTRL_TUNED_CLK for tuning. It is a preparation and will be used by Fujitsu SDHCI controller f_sdh30 driver. Signed-off-by: Vincent Yang <Vincent.Yang@tw.fujitsu.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: use pipeline mmc requests to improve performanceHaibo Chen2015-01-191-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN. This patch complete the API 'post_req' and 'pre_req' in sdhci host side, Test Env: 1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller. 2. Test command: $ echo 1 > /proc/sys/vm/drop_caches write to sd card: $ dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=2000 conv=fsync read the sd card: $ dd if=/dev/mmcblk0 of=/dev/null bs=1M count=2000 3. TOSHIBA 16GB SD3.0 card, running at 4 bit, SDR104 @ 198MHZ Performance with and without this patch: ------------------------------------------------- | | read speed | write speed | |------------------------------------------------ | with this patch | ~76.7 MB/s | ~23.3 MB/s | |------------------------------------------------ |without this patch | ~60.5 MB/s | ~22.5 MB/s | ------------------------------------------------- 4. SanDisk 8GB SD3.0 card, running at 4 bit, DDR50 @ 50MHZ Performance with and without this patch: ------------------------------------------------- | | read speed | write speed | |------------------------------------------------ | with this patch | ~40.5 MB/s | ~15.6 MB/s | |------------------------------------------------ |without this patch | ~36.1 MB/s | ~14.1 MB/s | ------------------------------------------------- 5. Kingston 8GB SD2.0 card, running at 4 bit, High-speed @ 50MHZ Performance with and without this patch: ------------------------------------------------- | | read speed | write speed | |------------------------------------------------ | with this patch | ~22.7 MB/s | ~8.2 MB/s | |------------------------------------------------ |without this patch | ~21.3 MB/s | ~8.0 MB/s | ------------------------------------------------- 6. About eMMC, Sandisk 8GB eMMC on i.MX6DL-sabresd board, CPU @ 792MHZ, eMMC running at 8 bit, DDR52 @ 52MHZ. Performance with and without this patch: ------------------------------------------------- | | read speed | write speed | |------------------------------------------------ | with this patch | ~37.3 MB/s | ~10.5 MB/s | |------------------------------------------------ |without this patch | ~33.4 MB/s | ~10.5 MB/s | ------------------------------------------------- Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Disable re-tuning for HS400Adrian Hunter2015-01-121-0/+1
| | | | | | | | | | | | | | | | | | | | | Re-tuning for HS400 mode must be done in HS200 mode. Currently there is no support for that. That needs to be reflected in the code. Specifically, if tuning is executed in HS400 mode then return an error, and do not start the tuning timer if HS200 tuning is being done prior to switching to HS400. Note that periodic re-tuning is not expected to be needed for HS400 but re-tuning is still needed after the host controller has lost power. In the case of suspend/resume that is not necessary because the card is fully re-initialised. That just leaves runtime suspend/resume with no support for HS400 re-tuning. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Add HS400 support to SDHCI driverAdrian Hunter2014-11-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | MMC core already has support for HS400. Add HS400 support to SDHCI driver. The SDHC Standard specification does not define HS400 so consequently HS400 support is non-standard. However HS400 is not selected without the host controller setting the corresponding capability flags so host controllers not yet supporting HS400 will not be affected. To support that, a quirk SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 is introduced to enable the use of capabilities register reserved bit-63 to indicate HS400 support. Because HS400 is non-standard for SDHCI, it is possible that different vendors will do things in different ways. However HS200 support faced the same issue but currently there is only one solution. As such, no attempt has been made to provide for alternate HS400 solutions except for SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Add a quirk for AMD SDHC transfer mode register need to be ↵Vincent Wan2014-11-261-0/+2
| | | | | | | | | | | | | | | cleared for cmd without data SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms Signed-off-by: Vincent Wan <vincent.wan@amd.com> Signed-off-by: Wan Zongshun <mcuos.com@gmail.com> Signed-off-by: Arindam Nath <arindam.nath@amd.com> Tested-by: Vikram B <vikram.b@amd.com> Tested-by: Raghavendra Swamy <raghavendra.swamy@amd.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Add 64-bit ADMA supportAdrian Hunter2014-11-101-0/+3
| | | | | | | | | | | | | | | | | | | Add 64-bit ADMA support including: - add 64-bit ADMA descriptor - add SDHCI_USE_64_BIT_DMA flag - set upper 32-bits of DMA addresses - ability to select 64-bit ADMA - ability to use 64-bit ADMA sizes and alignment - display "ADMA 64-bit" when host is added It is assumed that a 64-bit capable device has set a 64-bit DMA mask and *must* do 64-bit DMA. A driver has the opportunity to change that during the first call to ->enable_dma(). Similarly SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to implement. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Parameterize ADMA sizes and alignmentAdrian Hunter2014-11-101-0/+7
| | | | | | | | | | | | | In preparation for 64-bit ADMA, parameterize ADMA sizes and alignment. 64-bit ADMA has a larger descriptor because it contains a 64-bit address instead of a 32-bit address. Also data must be 8-byte aligned instead of 4-byte aligned. Consequently, sdhci_host members are added for descriptor, table, and buffer sizes and alignment. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Use 'void *' for not 'u8 *' for ADMA dataAdrian Hunter2014-11-101-2/+2
| | | | | | | | | | | It is kernel-style to use 'void *' for anonymous data. This is being applied to the ADMA bounce buffer which contains unaligned bytes, and to the ADMA descriptor table which will contain 32-bit ADMA descriptors or 64-bit ADMA descriptors when support is added. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Rename adma_desc to adma_tableAdrian Hunter2014-11-101-1/+1
| | | | | | | | | | In preparation for 64-bit ADMA, rename adma_desc to adma_table. That is because members will be added for descriptor size and table size, so using adma_desc (which is the table) is confusing. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Add quirk for always getting TC with stop cmdAdrian Hunter2014-10-031-0/+2
| | | | | | | | | Add a quirk for a host controller that always sets a Transfer Complete interrupt status for the stop command even when a busy response is not indicated. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: handle busy-end interrupt during commandChanho Min2014-09-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is fully legal for a controller to start handling busy-end interrupt before it has signaled that the command has completed. So make sure we do things in the proper order, Or it results that command interrupt is ignored so it can cause unexpected operations. This is founded at some toshiba emmc with the bellow warning. "mmc0: Got command interrupt 0x00000001 even though no command operation was in progress." This issue has been also reported by Youssef TRIKI: It is not specific to Toshiba devices, and happens with eMMC devices as well as SD card which support Auto-CMD12 rather than CMD23. Also, similar patch is submitted by: Gwendal Grignou <gwendal@chromium.org> Changes since v1: Fixed conflict with the next of git.linaro.org/people/ulf.hansson/mmc.git and Tested if issue is fixed again. Signed-off-by: Hankyung Yu <hankyung.yu@lge.com> Signed-off-by: Chanho Min <chanho.min@lge.com> Tested-by: Youssef TRIKI <youssef.triki@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Use mmc core regulator infrastuctureTim Kryger2014-07-091-3/+0
| | | | | | | | | | | | | | | | Switch the common SDHCI code over to use mmc_host's regulator pointers and remove the ones in the sdhci_host structure. Additionally, use the common mmc_regulator_get_supply function to get the regulators and set the ocr_avail mask. This change sets the ocr_avail directly based upon the voltage ranges supported which ensures ocr_avail is set correctly while allowing the use of regulators that can't provide exactly 1.8v, 3.0v, or 3.3v. Signed-off-by: Tim Kryger <tim.kryger@gmail.com> Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: track whether preset mode is currently enabled in hardwareRussell King2014-05-221-0/+1
| | | | | | | | | | | | Track whether preset mode is currently enabled in hardware, and use that when making decisions elsewhere in the code rather than reading the register and checking the bit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: cache timing information locallyRussell King2014-05-221-0/+2
| | | | | | | | | | | | | | Rather than reading back the timing information from the registers, cache it locally. This allows implementations to translate the UHS timing by overriding the set_uhs_signaling() method as required without also having to emulate the SDHCI_HOST_CONTROL2 register. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> [Ulf Hansson] Resolved conflict Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: convert sdhci_set_clock() into a library functionRussell King2014-05-221-2/+0
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: move FSL ESDHC reset handling quirk into esdhc codeRussell King2014-05-221-2/+0
| | | | | | | | | | | | The Freescale esdhc driver is the only driver which needs the interrupt registers restored after a reset. Move this quirk to be part of the ESDHC driver implementation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: more efficient interrupt enable register handlingRussell King2014-05-221-0/+3
| | | | | | | | | | | Rather than wasting cycles read-modify-writing the interrupt enable registers, cache the value locally instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: push card_tasklet into threaded irq handlerRussell King2014-05-221-2/+1
| | | | | | | | | | | | There's no requirement to have the card tasklet separate now that we have a threaded interrupt handler, so kill this and move the called code into the threaded part of the handler. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: convert to new SDIO IRQ handlingRussell King2014-05-221-0/+2
| | | | | | | | | | | | | | | | | | Use a generic threaded interrupt handler for SDIO interrupt handling, rather than allowing the SDIO core code to buggily spawn its own thread. This results in host drivers to be more in control of how SDIO interrupts are acknowledged in the hardware, rather than having the internals of the SDIO core placed upon them, possibly resulting in sub-standard handling. At least one SDHCI implementation specifies a very specific sequence to deal with a card interrupt. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: add support for realtek rts5250Micky Ching2014-02-221-0/+2
| | | | | | | | Add support for realtek rts5250 pci card reader. The card reader has some problems with DDR50 mode, so add a new quirks2 for broken ddr50. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: add quirk for broken HS200 supportDavid Cohen2014-01-131-0/+2
| | | | | | | | | | This patch defines a quirk for platforms unable to enable HS200 support. Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Reviewed-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Acked-by: Dong Aisheng <b29396@freescale.com> Cc: stable <stable@vger.kernel.org> # [3.13] Signed-off-by: Chris Ball <chris@printf.net>
* mmc: sdhci: get voltage from sdhc hostHaijun Zhang2013-08-261-0/+1
| | | | | | | | | | We use host->ocr_mask to hold the voltage get from device-tree node, In case host->ocr_mask was available, we use host->ocr_mask as the final available voltage can be used by MMC/SD/SDIO card. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Reviewed-by: Anton Vorontsov <anton@enomsg.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: esdhc: Fix bug when writing to SDHCI_HOST_CONTROL registerOded Gabbay2013-07-051-0/+2
| | | | | | | | | | | | | | | | The P2020 has a non-standard implementation of the SDHCI_HOST_CONTROL register. This patch adds a QUIRK in the SDHCI header to signal that a host controller has a non-standard SDHCI_HOST_CONTROL register. The patch adds a check to the function esdhc_writeb in file sdhci-of-esdhc.c, where it checks if the write is done to the SDHCI_HOST_CONTROL register and th host has the above mentioned QUIRK, then the function simply returns instead of writing to the register. The patch also detects if the processor is P2020 (by looking in dev tree) and if so, adds the QUIRK to the host->quirk2 Signed-off-by: Oded Gabbay <ogabbay@advaoptical.com> Reviewed-by: Anton Vorontsov <anton@enomsg.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: fix caps2 for HS200Giuseppe CAVALLARO2013-06-271-1/+1
| | | | | | | | | | | | | Although the HC supports HS200 (eMMC) the caps2 are always zero; this means there's no way to use the super speed mode (when init the card). If the HC support SDR104, for SD3.0, so it also supports HS200 for eMMC and this patch just sets the MMC_CAP2_HS200 in the host caps2 field. Reported-by: Youssef Triki <youssef.triki@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: Philip Rakity <prakity@nvidia.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: add ability to stay runtime-resumed if the card is powered upAdrian Hunter2013-05-261-0/+2
| | | | | | | | | | If card power is dependent on SD bus power then the host controller must not be runtime suspended while the card is powered up. Add the ability to stay runtime-resumed in that case and enable it with a new quirk SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: enhance preset value functionKevin Liu2013-02-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4d55c5a1 ("mmc: sdhci: enable preset value after uhs initialization") added preset value support and enabled it by default during sd card init. Below are the enhancements introduced by this patch: 1. In current code, preset value is enabled after setting clock finished, which means the clock is manually set by driver firstly and then suddenly switched to preset value at this point. So the first setting is useless and unnecessary. What's more, the first clock setting may differ from the preset one. The better way is enable preset value just after switch to UHS mode so the preset value can take effect immediately. So move preset value enable from mmc_sd_init_card to sdhci_set_ios which will be called during set timing. 2. In current code, preset value is disabled at the beginning of mmc_attach_sd. It's too late since low freq (400khz) should be set in mmc_power_up. So move preset value disable to sdhci_set_ios which will be called during power up. 3. host->clock and ios->drv_type should also be updated according to the preset value if it's enabled. Current code missed this. 4. This patch also introduce a quirk to disable preset value in case preset value doesn't work. This patch has been verified on sdhci-pxav3 platform with both preset enabled and disabled. Signed-off-by: Kevin Liu <kliu5@marvell.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: add quirk for lack of 1.8v supportDaniel Drake2012-12-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The OLPC XO-1.75 laptop includes a SDHCI controller which is 1.8v capable, and it truthfully reports so in its capabilities. This alternate voltage is used for driving new "UHS-I" SD cards at their full speed. However, what the controller doesn't know is that the motherboard physically doesn't have a 1.8v supply available. Add a quirk so that systems such as this one can override disable 1.8v support, adding support for UHS-I cards (by running them at 3.3v). This avoids a problem where the system would first try to run the card at 1.8v, fail, and then not be able to fully reset the card to retry at the normal 3.3v voltage. This is more appropriate than using the MISSING_CAPS quirk, which is intended for cases where the SDHCI controller is actually lying about its capabilities, and would force us to somehow override both caps words from another source. Signed-off-by: Daniel Drake <dsd@laptop.org> Reviewed-by: Philip Rakity <prakity@nvidia.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: Standardise capability typeLee Jones2012-12-061-2/+2
| | | | | | | | | There are discrepancies with regards to how MMC capabilities are carried throughout the subsystem. Let's standardise them to eliminate any confusion. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci-of-esdhc: disable CMD23 for some Freescale SoCsJerry Huang2012-11-071-0/+1
| | | | | | | | | | | | | CMD23 causes lots of errors in kernel on some freescale SoCs (P1020, P1021, P1022, P1024, P1025 and P4080) when MMC card used, which is because these controllers does not support CMD23, even on the SoCs which declares CMD23 is supported. Therefore, we'll not use CMD23. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: Add regulator support for vccq (voltage regualor)Philip Rakity2012-09-041-1/+2
| | | | | | | | | On some systems the host controller does not support vccq signaling. This is supplied by a dedicated regulator (vqmmc). Add support for this regulator. Signed-off-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: Introduce new flag SDHCI_USING_RETUNING_TIMERAaron Lu2012-07-221-0/+1
| | | | | | | | | | | | | | | | | | | | | Add a new flag of SDHCI_USING_RETUNING_TIMER to represent if the host is using a retuning timer for the card inserted. This flag is set when the host does tuning the first time for the card and the host's retuning mode is 1. This flag is used afterwards whenever needs to decide if the host is currently using a retuning timer. This flag is cleared when the card is removed in sdhci_reinit. The set/clear of the flag and the start/stop of the retuning timer is associated with the card's init/remove time, so there is no need to touch it when the host is to be removed as at that time the card should have already been removed. Signed-off-by: Aaron Lu <aaron.lu@amd.com> Reviewed-by: Girish K S <girish.shivananjappa@linaro.org> Reviewed-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: Allow caps[1] to be set via SDHCI_QUIRK_MISSING_CAPSPhilip Rakity2012-07-221-1/+2
| | | | | | | | | | | | | | | Currently only the capability_0 register can be set if SDHCI_QUIRK_MISSING_CAPS is defined. This is a problem when the capability_1 register also needs changing. Use the quirk SDHCI_QUIRK_MISSING_CAPS to allow both registers to be set. Redefining caps[1] is useful when the board design does not support 1.8v vccq so UHS modes are not available. The code that calls sdhci_add_host can then detect this condition and adjust the caps so the UHS mode will not be attempted on UHS cards. Signed-off-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: add quirk for keeping card power during suspendAdrian Hunter2012-03-271-0/+2
| | | | | | | | | | Add quirk SDHCI_QUIRK2_HOST_OFF_CARD_ON to cater for the case when the card keeps power during suspend but the host controller does not i.e. the card power is not controlled by the host controller. In that case, the controller must be fully reset on resume. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: host: Adds support for eMMC 4.5 HS200 modeGirish K S2012-01-121-0/+1
| | | | | | | | | This patch adds support for the HS200 mode on the host side. Also enables the tuning feature required when the HS200 mode is selected. Signed-off-by: Girish K S <girish.shivananjappa@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci-pci: remove SDHCI_QUIRK2_OWN_CARD_DETECTIONAdrian Hunter2012-01-111-2/+0
| | | | | | | | | Even if a driver provides separate card detection, an interrupt is still needed to abort mmc requests that are in progress. SDHCI_QUIRK2_OWN_CARD_DETECTION prevents that, so remove it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci-pci: add runtime pm supportAdrian Hunter2011-10-261-0/+8
| | | | | | | | | | | | | Ths patch allows runtime PM for sdhci-pci, runtime suspending after inactivity of 50ms and ensuring runtime resume before SDHC registers are accessed. During runtime suspend, interrupts are masked. The host controller state is restored at runtime resume. For Medfield, the host controller's card detect mechanism is supplanted by an always-on GPIO which provides for card detect wake-up. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: Standardize header file inclusion checks.Robert P. J. Day2011-07-201-3/+3
| | | | | | | | | Standardize the checks for multiple MMC header file inclusion, including adding comments to terminating #endif's, and fixing one incorrect comment. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: Auto-CMD23 support.Andrei Warkentin2011-05-251-0/+1
| | | | | | | | Enables Auto-CMD23 support where available (SDHCI 3.0 controllers) Signed-off-by: Andrei Warkentin <andreiw@motorola.com> Tested-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: Implement MMC_CAP_CMD23 for SDHCI.Andrei Warkentin2011-05-251-0/+1
| | | | | | | | Implements support for multiblock transfers bounded by SET_BLOCK_COUNT (CMD23). Signed-off-by: Andrei Warkentin <andreiw@motorola.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: add support for retuning mode 1Arindam Nath2011-05-241-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Host Controller v3.00 can support retuning modes 1,2 or 3 depending on the bits 46-47 of the Capabilities register. Also, the timer count for retuning is indicated by bits 40-43 of the same register. We initialize timer_list for retuning the first time we execute tuning procedure. This condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since retuning mode 1 sets a limit of 4MB on the maximum data length, we set max_blk_count appropriately. Once the tuning timer expires, we set SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning procedure before sending the next command. We need to restore mmc_request structure after executing retuning procedure since host->mrq is used inside the procedure to send CMD19. We also disable and re-enable this flag during suspend and resume respectively, as per the spec v3.00. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: add support for programmable clock modeArindam Nath2011-05-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sd: add support for tuning during uhs initializationArindam Nath2011-05-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: Fix read-only detection with JMicron 388 chipTakashi Iwai2011-05-241-0/+2
| | | | | | | | | | | | | | | | | On HP laptops with JMicron 388 chip, the write-locked SD card isn't detected correctly as read-only in many cases. This is because the PRESENT_STATE register becomes unsable just after plugging, and it returns the WRITE_PROTECT bit wrongly at the first read. This patch fixes the read-only detection by adding a new sdhci quirk indicating to check the register more intensively with a relatively long delay. The patch is tested with 2.6.39-rc4 kernel. Cc: Aries Lee <arieslee@jmicron.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: add quirk for max len ADMA descriptorsOlof Johansson2011-01-081-0/+2
| | | | | | | | | Some controllers misparse segment length 0 as being 0, not 65536. Add a quirk to deal with it. Signed-off-by: Olof Johansson <olof@lixom.net> Reviewed-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: Add support for JMicron 388 SD/MMC controllerTakashi Iwai2011-01-081-0/+4
| | | | | | | | | | | | | | | | | | | | | JMicron 388 SD/MMC combo controller supports the 1.8V low-voltage for SD, but MMC doesn't work with the low-voltage, resulting in an error at probing. This patch adds the support for multiple voltage mask per device type, so that SD works with 1.8V while MMC forces 3.3V. Here new ocr_avail_* fields for each device are introduced, so that the actual OCR mask is switched dynamically. Also, the restriction of low-voltage in core/sd.c is removed when the bit is allowed explicitly via ocr_avail_sd mask. This patch was rewritten from scratch based on Aries' original code. Signed-off-by: Aries Lee <arieslee@jmicron.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Reviewed-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* mmc: sdhci: split up sdhci.h for sdhci-pltfm usersGiuseppe Cavallaro2010-10-231-0/+144
Some platforms based on sdhci-pltfm need to set their own quirks. Previously to this patch, the quirks were in drivers/mmc/host/sdhci.h. This patch splits drivers/mmc/host/sdhci.h into two parts: * drivers/mmc/host/sdhci.h includes the HC registers and I/O accessors. * include/linux/mmc/sdhci.h includes the sdhci structure and quirks. Instead of including drivers/mmc/host/sdhci.h, -pltfm drivers should now include include/linux/mmc/sdhci.h and include/linux/sdhci-pltfm.h. This patch avoids adding/changing the calls/flags in the sdhci_pltfm_data structure. It has been tested on STM platforms (e.g. STx7106, STx7108, STx5206) where the driver is configured and used as shown in the example below: [snip] static int mmc_pad_resources(struct sdhci_host *sdhci) { if (!devm_stm_pad_claim(sdhci->mmc->parent, &stx7108_mmc_pad_config, dev_name(sdhci->mmc->parent))) return -ENODEV; return 0; } static struct sdhci_pltfm_data stx7108_mmc_platform_data = { .init = mmc_pad_resources, .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, }; static struct platform_device stx7108_mmc_device = { .name = "sdhci", [snip] Note: drivers/mmc/host/sdhci.h now also includes linux/mmc/sdhci.h, and no modifications should be needed on other sdhci-<XXX> drivers. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>
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