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* sh: migrate to arch/sh/include/Paul Mundt2008-07-291-152/+0
| | | | | | | | | | | | | This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Stub in page_table_range_init() on nommu.Paul Mundt2008-01-281-0/+2
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Clean up places that make 29-bit physical assumptions.Stuart Menefy2008-01-281-1/+7
| | | | | Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: SH-5 uses a 64-bit PTE_MAGNITUDE, as X2 TLB.Paul Mundt2008-01-281-1/+1
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Split out pgtable.h in to _32 and _64 variants.Paul Mundt2008-01-281-480/+11
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up VMALLOC_START for SH-5.Paul Mundt2008-01-281-0/+4
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Split out 29-bit and 32-bit physical mode definitions.Paul Mundt2008-01-281-0/+17
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up PAGE_KERNEL_PCC() for nommu.Paul Mundt2007-11-071-1/+3
| | | | | | | PAGE_KERNEL_PCC() takes two arguments, which weren't reflected in the nommu case. Fix it up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Correct pte_page() breakage.Paul Mundt2007-10-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As noted by David: pte_page() is a macro defined as follows; include/asm-sh/pgtable.h #define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK) include/asm-sh/page.h #define phys_to_page(phys) (pfn_to_page(phys >> PAGE_SHIFT)) So as you can see the phys_to_page() macro doesn't wrap the 'phys' parameter in parentheses so we end up with; pte_val(x)&PTE_PHYS_MASK >> PAGE_SHIFT Which is not what we wanted as '>>' has a higher precedence than bitwise AND. I dug into the git repository and I believe this bug was added with this commit (104b8deaa5c0144cccfc7d914413ff80c7176af1); 2006-03-27 KAMEZAWA Hiroyuki [PATCH] unify pfn_to_page: sh pfn_to_page -#define phys_to_page(phys) (mem_map + (((phys)-__MEMORY_START) >> PAGE_SHIFT)) -#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + __MEMORY_START) +#define phys_to_page(phys) (pfn_to_page(phys >> PAGE_SHIFT)) +#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) Reported-by: David ADDISON <david.addison@st.com> Reported-by: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up extended mode TLB for SH-X2+ cores.Paul Mundt2007-09-211-50/+62
| | | | | | | | | | | | | | | | The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot, correspondingly, the PGD also has to be 64-bits, so fix that up. The kernel and user permission bits really are decoupled in early cuts of the silicon, which means that we also have to set corresponding kernel permissions on user pages or we end up with user pages that the kernel simply can't touch (!). Finally, with those things corrected, really enable MMUCR.ME and correct the PTEA value (this simply needs to be the upper 32-bits of the PTE, with the size and protection bit encoding). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Support explicit L1 cache disabling.Paul Mundt2007-09-211-1/+2
| | | | | | | | | This reworks the cache mode configuration in Kconfig, and allows for explicit selection of write-back/write-through/off configurations. All of the cache flushing routines are optimized away for the off case. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Reclaim beginning of P3 space for vmalloc area.Paul Mundt2007-07-251-5/+1
| | | | | | | | The first 1MB of P3 space was reserved and used for page colouring, as we've reworked that to use fixmaps, we can reclaim the space and hand it back to VMALLOC_START. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* page table handling cleanupJan Beulich2007-07-161-12/+0
| | | | | | | | | | | | Kill pte_rdprotect(), pte_exprotect(), pte_mkread(), pte_mkexec(), pte_read(), pte_exec(), and pte_user() except where arch-specific code is making use of them. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: Christoph Hellwig <hch@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Clean up mostly unused IOSPACE macrosDavid Gibson2007-05-081-4/+0
| | | | | | | | | | | | | | | Most architectures defined three macros, MK_IOSPACE_PFN(), GET_IOSPACE() and GET_PFN() in pgtable.h. However, the only callers of any of these macros are in Sparc specific code, either in arch/sparc, arch/sparc64 or drivers/sbus. This patch removes the redundant macros from all architectures except sparc and sparc64. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* sh: Revert lazy dcache writeback changes.Paul Mundt2007-03-051-0/+5
| | | | | | | These ended up causing too many problems on older parts, revert for now.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Revert TLB miss fast-path changes that broke PTEA parts.Paul Mundt2007-02-141-1/+1
| | | | | | | | This ended up causing problems for older parts (particularly ones using PTEA). Revert this for now, it can be added back in once it's had some more testing. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Lazy dcache writeback optimizations.Paul Mundt2007-02-131-5/+0
| | | | | | | | | | | | | | | This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: More tidying for large base pages.Paul Mundt2007-02-131-2/+2
| | | | | | | | There were a few more things that needed fixing up, namely THREAD_SIZE and the TLB miss handler where certain PTRS_PER_PGD == PTRS_PER_PTE assumptions were being made. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: landisk board build fixes.Paul Mundt2006-12-121-1/+1
| | | | | | Get the landisk board building again.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Reworked swap cache entry encoding for SH-X2 MMU.Paul Mundt2006-12-121-6/+41
| | | | | | | | | | | | | In the 64-bit PTE case there's no point in restricting the encoding to the low bits of the PTE, we can instead bump all of this up to the high 32 bits and extend PTE_FILE_MAX_BITS to 32, adopting the same convention used by x86 PAE. There's a minor discrepency between the number of bits used for the swap type encoding between 32 and 64-bit PTEs, but this is unlikely to cause any problem given the extended offset. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup pte_mkhuge() build failure.Paul Mundt2006-12-061-0/+8
| | | | | | | | When hugetlbpage support isn't enabled, this can be bogus. Wrap it back in _PAGE_FLAGS_HARD to avoid changes to the base PTE when not aiming for larger sizes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup various PAGE_SIZE == 4096 assumptions.Paul Mundt2006-12-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | There were a number of places that made evil PAGE_SIZE == 4k assumptions that ended up breaking when trying to play with 8k and 64k page sizes, this fixes those up. The most significant change is the way we load THREAD_SIZE, previously this was done via: mov #(THREAD_SIZE >> 8), reg shll8 reg to avoid a memory access and allow the immediate load. With a 64k PAGE_SIZE, we're out of range for the immediate load size without resorting to special instructions available in later ISAs (movi20s and so on). The "workaround" for this is to bump up the shift to 10 and insert a shll2, which gives a bit more flexibility while still being much cheaper than a memory access. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: TLB miss fast-path optimizations.Stuart Menefy2006-12-061-3/+3
| | | | | | | | Handle simple TLB miss faults which can be resolved completely from the page table in assembler. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pmd rework.Stuart Menefy2006-12-061-27/+11
| | | | | | | | | Remove extra bits from the pmd structure and store a kernel logical address rather than a physical address. This allows it to be directly dereferenced. Another piece of wierdness inherited from x86. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Preliminary support for SH-X2 MMU.Paul Mundt2006-12-061-67/+294
| | | | | | | | | | | | | | | | | | | This adds some preliminary support for the SH-X2 MMU, used by newer SH-4A parts (particularly SH7785). This MMU implements a 'compat' mode with SH-X MMUs and an 'extended' mode for SH-X2 extended features. Extended features include additional page sizes (8kB, 4MB, 64MB), as well as the addition of page execute permissions. The extended mode attributes are placed in a second data array, which requires us to switch to 64-bit PTEs when in X2 mode. With the addition of the exec perms, we also overhaul the mmap prots somewhat, now that it's possible to handle them more intelligently. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Calculate shm alignment at runtime.Paul Mundt2006-09-271-2/+0
| | | | | | | Set the SHM alignment at runtime, based off of probed cache desc. Optimize get_unmapped_area() to only colour align shared mappings. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Free up some and document PTEL flags.Paul Mundt2006-09-271-31/+45
| | | | | | | | Drop _PAGE_SHARED/_PAGE_U0_SHARED and document Linux PTE encodings in the PTEL value. Preserve the swap cache entry encoding semantics for now, though it will need rework to free up _PAGE_WT from _PAGE_FILE. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: page table alloc cleanups and page fault optimizations.Paul Mundt2006-09-271-27/+53
| | | | | | | | | | | Cleanup of page table allocators, using generic folded PMD and PUD helpers. TLB flushing operations are moved to a more sensible spot. The page fault handler is also optimized slightly, we no longer waste cycles on IRQ disabling for flushing of the page from the ITLB, since we're already under CLI protection by the initial exception handler. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* [PATCH] Standardize pxx_page macrosDave McCracken2006-09-261-2/+2
| | | | | | | | | | | | | | | | | | | | | One of the changes necessary for shared page tables is to standardize the pxx_page macros. pte_page and pmd_page have always returned the struct page associated with their entry, while pte_page_kernel and pmd_page_kernel have returned the kernel virtual address. pud_page and pgd_page, on the other hand, return the kernel virtual address. Shared page tables needs pud_page and pgd_page to return the actual page structures. There are very few actual users of these functions, so it is simple to standardize their usage. Since this is basic cleanup, I am submitting these changes as a standalone patch. Per Hugh Dickins' comments about it, I am also changing the pxx_page_kernel macros to pxx_page_vaddr to clarify their meaning. Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Cc: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Don't include linux/config.h from anywhere else in include/David Woodhouse2006-04-261-1/+0
| | | | Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* [PATCH] fix remaining missing includesTim Schmielau2005-11-071-0/+2
| | | | | | | | | | Fix more include file problems that surfaced since I submitted the previous fix-missing-includes.patch. This should now allow not to include sched.h from module.h, which is done by a followup patch. Signed-off-by: Tim Schmielau <tim@physik3.uni-rostock.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] sh: pte_mkhuge() compile fix for !CONFIG_HUGETLB_PAGEPaul Mundt2005-11-071-0/+2
| | | | | | | | | | | | Presently it is bogus to call pte_mkhuge() outside of the CONFIG_HUGETLB_PAGE context, as the only processors that support _PAGE_SZHUGE do so in the hugetlbpage context only (and this is the only time that _PAGE_SZHUGE is even defined). SH-2 and SH-3 do not support huge pages at all, and so it is not possible to enable this. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] vm: remove unused/broken page_pte[_prot] macrosTejun Heo2005-10-301-2/+0
| | | | | | | | | | | | | | | | | | | | | | | This patch removes page_pte_prot and page_pte macros from all architectures. Some architectures define both, some only page_pte (broken) and others none. These macros are not used anywhere. page_pte_prot(page, prot) is identical to mk_pte(page, prot) and page_pte(page) is identical to page_pte_prot(page, __pgprot(0)). * The following architectures define both page_pte_prot and page_pte arm, arm26, ia64, sh64, sparc, sparc64 * The following architectures define only page_pte (broken) frv, i386, m32r, mips, sh, x86-64 * All other architectures define neither Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] feature removal of io_remap_page_range()Randy Dunlap2005-09-131-3/+0
| | | | | | | | | As written in Documentation/feature-removal-schedule.txt, remove the io_remap_page_range() kernel API. Signed-off-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] Hugepage consolidationDavid Gibson2005-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | A lot of the code in arch/*/mm/hugetlbpage.c is quite similar. This patch attempts to consolidate a lot of the code across the arch's, putting the combined version in mm/hugetlb.c. There are a couple of uglyish hacks in order to covert all the hugepage archs, but the result is a very large reduction in the total amount of code. It also means things like hugepage lazy allocation could be implemented in one place, instead of six. Tested, at least a little, on ppc64, i386 and x86_64. Notes: - this patch changes the meaning of set_huge_pte() to be more analagous to set_pte() - does SH4 need s special huge_ptep_get_and_clear()?? Acked-by: William Lee Irwin <wli@holomorphy.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] freepgt: arch FIRST_USER_ADDRESS 0Hugh Dickins2005-04-191-1/+1
| | | | | | | | | Replace misleading definition of FIRST_USER_PGD_NR 0 by definition of FIRST_USER_ADDRESS 0 in all the MMU architectures beyond arm and arm26. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+306
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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