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* usb: dwc3: gadget: remove unnecessary 'chain' variableFelipe Balbi2018-05-211-3/+1
| | | | | | Minor cleanup, no functional changes. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: remove PENDING handling from cleanup_completedFelipe Balbi2018-05-211-14/+0
| | | | | | | | We are trying to kick transfers on Isochronous endpoints in a more controlled manner now. And this ended up rendering this piece of code unnecessary. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: split scatterlist and linear handlersFelipe Balbi2018-05-211-26/+45
| | | | | | | instead of having one big loop, let's split it down into two smaller handlers: one for linear buffers and one for scatterlist. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: simplify isoc case on cleanup_completed_requestsFelipe Balbi2018-05-211-10/+3
| | | | | | Just a minor simplification, no functional changes. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: simplify queueing of isoc transfersFelipe Balbi2018-05-211-12/+6
| | | | | | | | After all the previous changes, it's now a lot clearer how isoc transfers should be managed. We don't need to try to End Transfers from ep_queue since that's already done by cleanup_requests. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: remove duplicated missed isoc handlingFelipe Balbi2018-05-213-35/+3
| | | | | | | Now, this part of the code is duplicated and brings no extra value to the driver. Let's remove it. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: check for Missed Isoc from event statusFelipe Balbi2018-05-212-5/+14
| | | | | | | | | | In case we get an event with status set to Missed Isoc, this means we have missed an isochronous interval and should issue End Transfer command and wait for the following XferNotReady. Let's do that early, rather than late. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: remove unnecessary 'ioc' variableFelipe Balbi2018-05-211-6/+1
| | | | | | It's only written to, never read. We can remove it now. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: make cleanup_completed_requests() return nothingFelipe Balbi2018-05-211-9/+4
| | | | | | We don't need to return a value anymore here. Let's remove it. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: remove DWC3_EP_BUSY flagFelipe Balbi2018-05-214-18/+6
| | | | | | It has no use anymore. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: start removing BUSY flagFelipe Balbi2018-05-211-2/+2
| | | | | | | By now, it has the same semantics as DWC3_EP_TRANSFER_STARTED, but that has a much more descriptive name. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: update dep->frame_number from XferInprogress tooFelipe Balbi2018-05-211-6/+13
| | | | | | | We will need an up-to-date frame_number from XferInProgress too when future patches improve our handling of Isoc endpoints. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: always use frame number from XferNotReadyFelipe Balbi2018-05-211-7/+5
| | | | | | | | | The core requires the extra two bits of information for properly scheduling Isochronous transfers. This means that we can't rely on __dwc3_gadget_get_frame(). Let's always cache uFrame number from XferNotReady instead. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: remove unnecessary 'dwc' parameterFelipe Balbi2018-05-211-36/+32
| | | | | | | | | | Endpoint handlers need to know about endpoints, not dwc. If they really need access to dwc (e.g. for printing error messages) we have a reference to it tucked inside the endpoint. This patch has no functional changes, it's simply moving things around. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: move handler closer to calling siteFelipe Balbi2018-05-211-11/+11
| | | | | | | Cleanup only, no functional changes. Just making code easier to follow. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: rename dwc3_gadget_start_isoc()Felipe Balbi2018-05-211-2/+2
| | | | | | | Cleanup only, no functional changes. This just matches the event name with its handler. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: remove some pointless checksFelipe Balbi2018-05-211-13/+1
| | | | | | | | We *KNOW* which events we enable for which endpoint types and we *KNOW* when they'll trigger. The endpoint type checks are pointless. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: remove allocated/queued request trackingFelipe Balbi2018-05-213-24/+8
| | | | | | That has never proven useful in any way. Just remove it. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: rename done_trbs and done_reqsFelipe Balbi2018-05-211-13/+16
| | | | | | | | | This patch simply renames two functions to more descriptive names so that it's easier to understand what they're doing. Cleanup only, no functional changes. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: don't kick transfer all the timeFelipe Balbi2018-05-211-11/+0
| | | | | | | | Instead of constantly calling kick transfer everything some event shows up, let's just rely on the fact that we send Update Transfer every time a new request is queued. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: rename dwc3_endpoint_transfer_complete()Felipe Balbi2018-05-211-6/+3
| | | | | | | | Now that we're making sure we don't have XferComplete events, we can rename this function to what it actually handles: dwc3_gadget_endpoint_transfer_in_progress() Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: XferComplete only for EP0Felipe Balbi2018-05-211-10/+1
| | | | | | | XferComplete is enabled only for the default control pipe, let's make that clear in the code. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: XferNotReady is Isoc-onlyFelipe Balbi2018-05-211-4/+6
| | | | | | | | We don't use XferNotReady for anything other than Default Control Pipe, which is handled in ep0.c, and Isochronous endpoints. Let's make that clear in the code. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: pre-issue Start Transfer for Interrupt EPs tooFelipe Balbi2018-05-211-2/+2
| | | | | | | | | | Interrupt endpoints behave much like Bulk endpoints with the exception that they are periodic. We can pre-issue Start Transfer exactly as we do for Bulk endpoints. While at that, remove one trailing blank line which is unnecessary. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: Correct the logic for queuing sgsAnurag Kumar Vulisha2018-05-212-3/+22
| | | | | | | | | | | | | | | The present code correctly fetches the req which were previously not queued from the started_list but fails to continue queuing from the sg where it previously stopped queuing (because of the unavailable TRB's). This patch correct's the code to continue queuing from the correct sg present in the sglist. For example, consider 5 sgs in req. Because of limited TRB's among the 5 sgs only 3 got queued. This patch corrects the code to start queuing from correct sg i.e 4th sg when the TRBs are available. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: Correct handling of scattergather listsAnurag Kumar Vulisha2018-05-212-3/+24
| | | | | | | | | | | The code logic in dwc3_prepare_one_trb() incorrectly uses the address and length fields present in req packet for mapping TRB's instead of using the address and length fields of scattergather lists. This patch correct's the code to use sg->address and sg->length when scattergather lists are present. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* USB: dwc3: get extcon device by OF graph bindingsAndrzej Hajda2018-05-161-6/+28
| | | | | | | | | extcon device is used to detect host/device connection. Since extcon OF property is deprecated, alternative method should be added. This method uses OF graph bindings to locate extcon. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: support clocks and resets for DWC3 coreMasahiro Yamada2018-05-162-2/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the clocks and resets are handled on the glue layer side instead of the DWC3 core. For simple cases, dwc3-of-simple.c takes care of arbitrary number of clocks and resets. The DT node structure typically looks like as follows: dwc3-glue { compatible = "foo,dwc3"; clocks = ...; resets = ...; ... dwc3 { compatible = "snps,dwc3"; ... }; } By supporting the clocks and the reset in the dwc3/core.c, it will be turned into a single node: dwc3 { compatible = "foo,dwc3", "snps,dwc3"; clocks = ...; resets = ...; ... } This commit adds the binding of clocks and resets specific to this IP. The number of clocks should generally be the same across SoCs, it is just some SoCs either tie clocks together or do not provide software control of some of the clocks. I took the clock names from the Synopsys datasheet: "ref" (ref_clk), "bus_early" (bus_clk_early), and "suspend" (suspend_clk). I found only one reset line in the datasheet, hence the reset-names property is omitted. Those clocks are required for new platforms. Enforcing the new binding breaks existing platforms since they specify clocks (and resets) in their glue layer node, but nothing in the core node. I listed such exceptional cases in the DT binding. The driver code has been relaxed to accept no clock. This change is based on the discussion [1]. I inserted reset_control_deassert() and clk_bulk_enable() before the first register access, i.e. dwc3_cache_hwparams(). [1] https://patchwork.kernel.org/patch/10284265/ Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: use local copy of resource to fix-up register offsetMasahiro Yamada2018-05-151-24/+8
| | | | | | | | | | | It is not a good idea to directly modify the resource of a platform device. Modify its local copy, and pass it to devm_ioremap_resource() so that we do not need to restore it in the failure path and the remove hook. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: core: Suspend PHYs on runtime suspend in host modeManu Gautam2018-05-151-3/+33
| | | | | | | | | | | | | Some PHY drivers (e.g. for Qualcomm QUSB2 and QMP PHYs) support runtime PM to reduce PHY power consumption during bus_suspend. Add changes to let core auto-suspend PHYs on host bus-suspend using GUSB2PHYCFG register if needed for a platform. Also perform PHYs runtime suspend/resume and let platform glue drivers e.g. dwc3-qcom handle remote wakeup during bus suspend by waking up devices on receiving wakeup event from PHY. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: Add Qualcomm DWC3 glue driverManu Gautam2018-05-154-1/+633
| | | | | | | | | | | | | | | | | | | | DWC3 controller on Qualcomm SOCs has a Qscratch wrapper. Some of its uses are described below resulting in need to have a separate glue driver instead of using dwc3-of-simple: - It exposes register interface to override vbus-override and lane0-pwr-present signals going to hardware. These must be updated in peripheral mode for DWC3 if vbus lines are not connected to hardware block. Otherwise RX termination in SS mode or DP pull-up is not applied by device controller. - pwr_events_irq_stat support to check if USB2 PHY is in L2 state before glue driver proceeds with suspend. - Support for wakeup interrupts lines that are asserted whenever there is any wakeup event on USB3 or USB2 bus. - Support to replace pip3 clock going to DWC3 with utmi clock for hardware configuration where SSPHY is not used with DWC3. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: of-simple: Add compatible for Allwinner H6 platformIcenowy Zheng2018-05-151-0/+1
| | | | | | | | Add compatible string to use this generic glue layer to support Allwinner H6 platform's dwc3 controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: gadget: never call ->complete() from ->ep_queue()Felipe Balbi2018-03-261-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a requirement which has always existed but, somehow, wasn't reflected in the documentation and problems weren't found until now when Tuba Yavuz found a possible deadlock happening between dwc3 and f_hid. She described the situation as follows: spin_lock_irqsave(&hidg->write_spinlock, flags); // first acquire /* we our function has been disabled by host */ if (!hidg->req) { free_ep_req(hidg->in_ep, hidg->req); goto try_again; } [...] status = usb_ep_queue(hidg->in_ep, hidg->req, GFP_ATOMIC); => [...] => usb_gadget_giveback_request => f_hidg_req_complete => spin_lock_irqsave(&hidg->write_spinlock, flags); // second acquire Note that this happens because dwc3 would call ->complete() on a failed usb_ep_queue() due to failed Start Transfer command. This is, anyway, a theoretical situation because dwc3 currently uses "No Response Update Transfer" command for Bulk and Interrupt endpoints. It's still good to make this case impossible to happen even if the "No Reponse Update Transfer" command is changed. Reported-by: Tuba Yavuz <tuba@ece.ufl.edu> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'usb-for-v4.17' of ↵Greg Kroah-Hartman2018-03-239-90/+839
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-testing Felipe writes: usb: changes for v4.17 merge window Quite a lot happened in this cycle, with a total of 95 non-merge commits. The most interesting parts are listed below: Synopsys has been adding better support for USB 3.1 to dwc3. The same series also sets g_mass_storage's max speed to SSP. Roger Quadros (TI) added support for dual-role using the OTG block available in some dwc3 implementations, this makes sure that AM437x can swap roles in runtime. We have a new SoC supported in dwc3 now - Amlogic Meson GX - thanks to the work of Martin Blumenstingl. We also have a ton of changes in dwc2 (51% of all changes, in fact). The most interesting part there is the support for Hibernation (a Synopsys PM feature). Apart from these, we have our regular set of non-critical fixes all over the place.
| * usb: dwc3: core: Fix broken system suspend/resume on AM437xRoger Quadros2018-03-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | On TI's AM437x, the DWC3 controller looses state after a system suspend/resume. We are re-initializing the controller but we miss restoring the PRTCAP register. This causes USB host to break on AM437x after a system suspend/resume. Fix this by restoring the PRTCAP register on system resume. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Check controller type before setting speedThinh Nguyen2018-03-221-1/+4
| | | | | | | | | | | | | | | | | | | | DWC_usb3 speed can only be set up to SuperSpeed. Limit the setting to SuperSpeed only should the value be higher. Otherwise, the controller will read an invalid speed value and set the device to an incorrect speed. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Dump LSP and BMU debug infoThinh Nguyen2018-03-222-0/+10
| | | | | | | | | | | | | | Dump LSP and BMU debug info. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Check for ESS TX/RX threshold configThinh Nguyen2018-03-222-0/+63
| | | | | | | | | | | | | | | | Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure with new fields to store these threshold configurations. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Add DWC_usb31 GTXTHRCFG reg fieldsThinh Nguyen2018-03-221-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new GTXTHRCFG bit field macros for DWC_usb31. The GTXTHRCFG register fields for DWC_usb31 is as follows: +-------+--------------------------+-----------------------------------+ | BITS | Name | Description | +=======+==========================+===================================+ | 31:27 | reserved | | | 26 | UsbTxPktCntSel | Async ESS transmit packet | | | | threshold enable | | 25:21 | UsbTxPktCnt | Async ESS transmit packet | | | | threshold count | | 20:16 | UsbMaxTxBurstSize | Async ESS Max transmit burst size | | 15 | UsbTxThrNumPktSel_HS_Prd | HS high bandwidth periodic | | | | transmit packet threshold enable | | 14:13 | UsbTxThrNumPkt_HS_Prd | HS high bandwidth periodic | | | | transmit packet threshold count | | 12:11 | reserved | | | 10 | UsbTxThrNumPktSel_Prd | Periodic ESS transmit packet | | | | threshold enable | | 9:5 | UsbTxThrNumPkt_Prd | Periodic ESS transmit packet | | | | threshold count | | 4:0 | UsbMaxTxBurstSize_Prd | Max periodic ESS TX burst size | +-------+--------------------------+-----------------------------------+ Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: gadget: Check IP revision for GRXTHRCFGThinh Nguyen2018-03-221-1/+5
| | | | | | | | | | | | | | | | | | DWC_usb31 controller has a different UsbRxPktCnt bit fields from GRXTHRCFG register. Check for DWC_usb31 IP revision to read the appropriate value. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fieldsThinh Nguyen2018-03-221-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register fields for DWC_usb31 is as follows: +-------+--------------------------+----------------------------------+ | BITS | Name | Description | +=======+==========================+==================================+ | 31:27 | reserved | | | 26 | UsbRxPktCntSel | Async ESS receive packet | | | | threshold enable | | 25:21 | UsbRxPktCnt | Async ESS receive packet | | | | threshold count | | 20:16 | UsbMaxRxBurstSize | Async ESS Max receive burst size | | 15 | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold enable | | 14:13 | UsbRxThrNumPkt_HS_Prd | HS high bandwidth periodic | | | | receive packet threshold count | | 12:11 | reserved | | | 10 | UsbRxThrNumPktSel_Prd | Periodic ESS receive packet | | | | threshold enable | | 9:5 | UsbRxThrNumPkt_Prd | Periodic ESS receive packet | | | | threshold count | | 4:0 | UsbMaxRxBurstSize_Prd | Max periodic ESS RX burst size | +-------+--------------------------+----------------------------------+ Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Check IP revision for GTXFIFOSIZThinh Nguyen2018-03-221-1/+4
| | | | | | | | | | | | | | | | DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF. Check for DWC_usb31 IP revision to read the appropriate bit fields. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fieldsThinh Nguyen2018-03-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM. The GTXFIFOSIZ register for DWC_usb31 is as follows: +-------+-----------+----------------------------------+ | BITS | Name | Description | +=======+===========+==================================+ | 31:16 | TXFSTADDR | Transmit FIFOn RAM Start Address | | 15 | TXFRAMNUM | Asynchronous/Periodic TXFIFO | | 14:0 | TXFDEP | TXFIFO Depth | +-------+-----------+----------------------------------+ Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Add SoftReset PHY synchonization delayThinh Nguyen2018-03-221-1/+12
| | | | | | | | | | | | | | | | | | From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST bit is cleared, we must wait at least 50ms before accessing the PHY domain (synchronization delay). Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: pci: Properly cleanup resourceThinh Nguyen2018-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | Platform device is allocated before adding resources. Make sure to properly cleanup on error case. Cc: <stable@vger.kernel.org> Fixes: f1c7e7108109 ("usb: dwc3: convert to pcim_enable_device()") Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Makefile: fix link error on randconfigFelipe Balbi2018-03-221-1/+1
| | | | | | | | | | | | | | | | | | If building a kernel without FTRACE but with TRACING, dwc3.ko fails to link due to missing trace events. Fix this by using the correct Kconfig symbol on Makefile. Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: ep0: remove redundant assignmentHeinrich Schuchardt2018-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In dwc3_request *r = NULL; r = A; the first assignment has no effect. Remove it. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Prevent indefinite sleep in _dwc3_set_mode during suspend/resumeRoger Quadros2018-03-131-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the following test we get stuck by sleeping forever in _dwc3_set_mode() after which dual-role switching doesn't work. On dra7-evm's dual-role port, - Load g_zero gadget driver and enumerate to host - suspend to mem - disconnect USB cable to host and connect otg cable with Pen drive in it. - resume system - we sleep indefinitely in _dwc3_set_mode due to. dwc3_gadget_exit()->usb_del_gadget_udc()->udc_stop()-> dwc3_gadget_stop()->wait_event_lock_irq() To fix this instead of waiting indefinitely with wait_event_lock_irq() we use wait_event_interruptible_lock_irq_timeout() and print and error message if there was a timeout. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: add dual role support using OTG blockRoger Quadros2018-03-133-28/+557
| | | | | | | | | | | | | | | | | | | | | | This is useful on platforms (e.g. TI AM437x) that don't have ID available on a GPIO but do have the OTG block. We can obtain the ID state via the OTG block and use it for dual-role switching. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: prevent setting PRTCAP to OTG from debugfsRoger Quadros2018-03-131-0/+3
| | | | | | | | | | | | | | | | | | | | We don't support PRTCAP == OTG yet, so prevent user from setting it via debugfs. Fixes: 41ce1456e1db ("usb: dwc3: core: make dwc3_set_mode() work properly") Cc: <stable@vger.kernel.org> # v4.12+ Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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