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path: root/drivers/usb/dwc3/core.c
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| * usb: dwc3: core: add dwc3_get_properties()Felipe Balbi2016-11-031-41/+49
| | | | | | | | | | | | | | | | This helper will be responsible for reading and parsing our properties. No functional changes in this patch, cleanup only. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: core: remove unnecessary alignmentFelipe Balbi2016-11-031-6/+2
| | | | | | | | | | | | Kernel will give us page aligned memory anyway. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: core: introduce dwc3_core_setup_global_control()Felipe Balbi2016-11-031-42/+48
| | | | | | | | | | | | | | | | This little helper will be used to setup anything related to GCTL register. There are no functional changes, this is a cleanup only patch. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: core: introduce dwc3_core_is_valid()Felipe Balbi2016-11-031-10/+22
| | | | | | | | | | | | | | This little helper will be used to make sure we're dealing with a valid Synopsys DWC3 or DWC3.1 core. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Add support for device L1 exitJohn Youn2016-11-031-0/+10
| | | | | | | | | | | | | | | | | | For the usb31 IP and from version 2.90a of the usb3 IP, the core supports HW exit from L1 in HS. Enable it, otherwise the controller may never exit from LPM to do a transfer. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: remove unused struct member dwc3->memLu Baolu2016-11-031-1/+0
| | | | | | | | | | | | | | Member @mem in struct dwc3 is not used in any places. Clean up it. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* | usb: dwc3: Fix error handling for core initVivek Gautam2016-10-311-3/+2
|/ | | | | | | | | | | | | | Fixing the sequence of events in dwc3_core_init() error exit path. dwc3_core_exit() call is also removed from the error path since, whatever it's doing is already done. Fixes: c499ff7 usb: dwc3: core: re-factor init and exit paths Cc: Felipe Balbi <felipe.balbi@linux.intel.com> Cc: Greg KH <gregkh@linuxfoundation.org> Cc: Stable <stable@vger.kernel.org> # 4.8+ Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* Merge tag 'usb-for-v4.9' of ↵Greg Kroah-Hartman2016-09-141-14/+108
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next Felipe writes: usb: patches for v4.9 merge window This time around we have 92 non-merge commits. Most of the changes are in drivers/usb/gadget (40.3%) with drivers/usb/gadget/function being the most active directory (27.2%). As for UDC drivers, only dwc3 (26.5%) and dwc2 (12.7%) have really been active. The most important changes for dwc3 are better support for scatterlist and, again, throughput improvements. While on dwc2 got some minor stability fixes related to soft reset and FIFO usage. Felipe Tonello has done some good work fixing up our f_midi gadget and Tal Shorer has implemented a nice API change for our ULPI bus. Apart from these, we have our usual set of non-critical fixes, spelling fixes, build warning fixes, etc.
| * usb: dwc3: Fix dr_mode validationThinh Nguyen2016-09-071-11/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch follows the similar fix in dwc2. See commit 5268ed9d2e3b ("usb: dwc2: Fix dr_mode validation") Currently, the dr_mode is only checked against the module configuration. It also needs to be checked against the hardware capablities. The driver now checks if both the module configuration and hardware are capable of the dr_mode value. If not, then it will issue a warning and fall back to a supported value. If it is unable to fall back to a suitable value, then the probe will fail. Behavior summary: module : actual HW config dr_mode : dr_mode --------------------------------- host host any : host host dev any : INVALID host otg any : host dev host any : INVALID dev dev any : dev dev otg any : dev otg host any : host otg dev any : dev otg otg any : dr_mode Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: Add ENDXFER command pollingJohn Youn2016-08-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | ENDXFER polling is available on version 3.10a and later of the DWC_usb3 (USB 3.0) controller. With this feature, the software can poll the CMDACT bit in the DEPCMD register after issuing an ENDXFER command. This feature is enabled by writing GUCTL2[14]. This feature is NOT available on the DWC_usb31 (USB 3.1) IP. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: core: Move the mode setting to the right placeBaolin Wang2016-08-251-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | When dwc3 core enters into suspend mode, the system (especially for mobile device) may power off the dwc3 controller for power saving, that will cause dwc3 controller lost the mode operation when resuming dwc3 core. Thus we can move the mode setting into dwc3_core_init() function to avoid this issue. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: add dis_del_phy_power_chg_quirkWilliam Wu2016-08-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu <william.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: make usb2 phy utmi interface configurableWilliam Wu2016-08-251-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support to configure the UTMI+ PHY with an 8- or 16-bit interface via DT. The UTMI+ PHY interface is a hardware capability, and it's platform dependent. Normally, the PHYIF can be configured during coreconsultant. But for some specific USB cores(e.g. rk3399 SoC DWC3), the default PHYIF configuration value is false, so we need to reconfigure it by software. Signed-off-by: William Wu <william.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: add dis_u2_freeclk_exists_quirkWilliam Wu2016-08-251-0/+5
| | | | | | | | | | | | | | | | | | | | Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu <william.wu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* | usb: dwc3: core: allow device to runtime_suspend several timesFelipe Balbi2016-08-221-0/+1
|/ | | | | | | | | | After going through runtime_suspend/runtime_resume cycle once we would be left with an unbalanced pm_runtime_get() call. Fix that by making sure that we try to suspend right after resuming so things are balanced and device can runtime_suspend again. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: core: cleanup IRQ resourcesRoger Quadros2016-06-211-14/+8
| | | | | | | | | | | | | | | | | | | | | Implementations might use different IRQs for host, gadget so use named interrupt resources to allow device tree to specify the interrupts. Following are the interrupt names Peripheral Interrupt - peripheral HOST Interrupt - host Maintain backward compatibility for a single named interrupt ("dwc3_usb3") for all interrupts as well as unnamed interrupt at index 0 for all interrupts. As platform_get_irq() variants are used, tackle the -EPROBE_DEFER case as well. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: fix runtime PM in error pathRoger Quadros2016-06-211-8/+18
| | | | | | | | | | | | | If there is a failure after pm_runtime_enable/get_sync() we need to call pm_runtime_disable/put_sync(). Otherwise it will lead to an unbalanced pm_runtime_enable() on the subsequent probe if the earlier probe bailed out due to -EPROBE_DEFER. pm_runtime_get_sync() can fail as well so deal with that case too. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: core: fixup dr_mode fallback selectionFelipe Balbi2016-06-211-2/+6
| | | | | | | We shouldn't change a host-only dwc3 to gadget-only if driver is built as gadget-only. Fix that up here. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: remove handling of platform dataHeikki Krogerus2016-06-201-35/+0
| | | | | | | | No more users for it. Tested-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: implement runtime PMFelipe Balbi2016-06-201-14/+134
| | | | | | | | | | | | | | | | | | | this patch implements the most basic pm_runtime support for dwc3. Whenever USB cable is dettached, then we will allow core to runtime_suspend. Runtime suspending will involve completely tearing down event buffers and require a full soft-reset of the IP. Note that a further optimization could be implemented once we decide to support hibernation, which is to allow runtime_suspend with cable connected when bus is in U3. That's subject to a separate patch, however. Tested-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: core: simplify suspend/resume operationsFelipe Balbi2016-06-201-54/+5
| | | | | | | | | | | | now that we have re-factored dwc3_core_init() and dwc3_core_exit() we can use them for suspend/resume operations. This will help us avoid some common mistakes when patching code when we have duplicated pieces of code doing the same thing. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: core: re-factor init and exit pathsFelipe Balbi2016-06-201-58/+60
| | | | | | | | | | | | | The idea of this patch is for dwc3_core_init() to abstract all the details about how to initialize dwc3 and dwc3_core_exit() to do the same for teardown. With this, we can simplify suspend/resume operations by a large margin and always know that we're going to start dwc3 from a known starting point. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: core: move fladj to dwc3 structureFelipe Balbi2016-06-201-9/+7
| | | | | | | | this patch is in preparation for some further re-factoring in dwc3 initialization. No functional changes. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: core: get rid of DWC3_PM_OPS macroFelipe Balbi2016-06-201-6/+2
| | | | | | | that macro is unnecessary and just adds pointless obfuscation. Let's remove it. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* Merge tag 'usb-for-v4.7' of ↵Greg Kroah-Hartman2016-04-281-66/+52
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next Felipe writes: usb: changes for v4.7 merge window Here's the big USB Gadget pull request. This time not as large as usual with only 57 non-merge commits. The most important part here is, again, all the work on dwc3. This time around we're treating all endpoints (except for control endpoint) exactly the same. They all have the same amount of TRBs on the ring, they all treat the ring as an actual ring with a link TRB pointing to the head, etc. We're also helping the host side burst (on SuperSpeed GEN1 or GEN2 at least) for as long as possible until the endpoint returns NRDY. Other than this big TRB ring rework on dwc3, we also have a dwc3-omap DMA initialization fix, some extra debugfs files to aid in some odd debug sessions and a complete removal of our FIFO resizing logic. We have a new quirk for some dwc3 P3 quirk in some implementations. The rest is basically non-critical fixes and the usual cleanups.
| * usb: dwc3: core: add fifo space helperFelipe Balbi2016-04-191-0/+14
| | | | | | | | | | | | | | | | | | | | this helper will be used, initially, to dump space of different queues and fifos in dwc3 to debugfs. Later, it'll be used to issue remote wakeup when we want to start a transfer and there's something in a TX FIFO. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: make dwc3_debugfs_init return value be voidDu, Changbin2016-04-191-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Debugfs init failure is not so important. We can continue our job on this failure. Also no break need for debugfs_create_file call failure. Signed-off-by: Du, Changbin <changbin.du@intel.com> [felipe.balbi@linux.intel.com : - remove out-of-memory message, we get that from OOM. - switch dev_err() to dev_dbg() ] Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: add disable receiver detection in P3 quirkRajesh Bhagat2016-04-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Some freescale QorIQ platforms require to disable receiver detection in P3 for correct detection of USB devices. If GUSB3PIPECTL(DISRXDETINP3) is set, Core will change PHY power state to P2 and then perform receiver detection. After receiver detection, Core will change PHY power state to P3. Same quirk would be added in dts file in future patches. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: drop ev_buffs arrayFelipe Balbi2016-04-141-9/+4
| | | | | | | | | | | | | | | | | | we will be using a single event buffer and that renders ev_buffs array unnecessary. Let's remove it in favor of a single pointer to a single event buffer. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: remove num_event_buffersFelipe Balbi2016-04-141-49/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | We never, ever route any of the other event buffers so we might as well drop support for them. Until someone has a real, proper benefit for multiple event buffers, we will rely on a single one. This also helps reduce memory footprint of dwc3.ko which won't allocate memory for the extra event buffers. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
| * usb: dwc3: drop FIFO resizing logicFelipe Balbi2016-04-141-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That FIFO resizing logic was added to support OMAP5 ES1.0 which had a bogus default FIFO size. I can't remember the exact size of default FIFO, but it was less than one bulk superspeed packet (<1024) which would prevent USB3 from ever working on OMAP5 ES1.0. However, OMAP5 ES1.0 support has been dropped by commit aa2f4b16f830 ("ARM: OMAP5: id: Remove ES1.0 support") which renders FIFO resizing unnecessary. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* | usb: dwc3: core: fix PHY handling during suspendFelipe Balbi2016-04-181-1/+22
|/ | | | | | | | | | | we need to power off the PHY during suspend and power it back on during resume. Signed-off-by: Felipe Balbi <balbi@kernel.org> [nsekhar@ti.com: fix call to usb_phy_set_suspend() in dwc3_suspend()] Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: core: improve reset sequenceFelipe Balbi2016-03-291-30/+18
| | | | | | | | | | | | | | | | | | | | According to Synopsys Databook, we shouldn't be relying on GCTL.CORESOFTRESET bit as that's only for debugging purposes. Instead, let's use DCTL.CSFTRST if we're OTG or PERIPHERAL mode. Host side block will be reset by XHCI driver if necessary. Note that this reduces amount of time spent on dwc3_probe() by a long margin. We're still gonna wait for reset to finish for a long time (default to 1ms max), but tests show that the reset polling loop executed at most 19 times (modprobe dwc3 && modprobe -r dwc3 executed 1000 times in a row). Suggested-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
* usb: dwc3: Validate the maximum_speed parameterJohn Youn2016-03-041-2/+16
| | | | | | | | Check that dwc->maximum_speed is set to a valid value. Also add an error when we use it later if we encounter an invalid value. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc3: Update maximum_speed for SuperSpeedPlusJohn Youn2016-03-041-4/+13
| | | | | | | | | | | | | If the maximum_speed is not set, set it to a known value, either SuperSpeed or SuperSpeedPlus based on the type of controller we are using. If we are on DWC_usb31 controller, check the PHY interface to see if it is capable of SuperSpeedPlus. Also this check is moved after dwc3_core_init() so that we can check dwc->revision. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* usb: dwc3: core: purge dev_dbg() callsFelipe Balbi2015-12-151-3/+5
| | | | | | | | The last few dev_dbg() messages are converted to tracepoints and we can finally ignore dev_dbg() messages during debug sessions. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: Add dis_enblslpm_quirkJohn Youn2015-10-091-0/+6
| | | | | | | | | Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Cc: <stable@vger.kernel.org> # v3.18+ Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: Support Synopsys USB 3.1 IPJohn Youn2015-10-091-2/+8
| | | | | | | | | | | | | | | | | | | | | | | This patch allows the dwc3 driver to run on the new Synopsys USB 3.1 IP core, albeit in USB 3.0 mode only. The Synopsys USB 3.1 IP (DWC_usb31) retains mostly the same register interface and programming model as the existing USB 3.0 controller IP (DWC_usb3). However the GSNPSID and version numbers are different. Add checking for the new ID to pass driver probe. Also, since the DWC_usb31 version number is lower in value than the full GSNPSID of the DWC_usb3 IP, we set the high bit to identify DWC_usb31 and to ensure the values are higher. Finally, add a documentation note about the revision numbering scheme. Any future revision checks (for STARS, workarounds, and new features) should take into consideration how it applies to both the 3.1/3.0 IP. Cc: <stable@vger.kernel.org> # v3.18+ Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: core: convert to unified device property interfaceHeikki Krogerus2015-09-271-26/+24
| | | | | | | | | No functional affect on existing platforms, but the driver is now ready to extract the properties also from ACPI tables as well as from DT. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: common: of_usb_get_dr_mode to usb_get_dr_modeHeikki Krogerus2015-09-271-1/+1
| | | | | | | | | By using the unified device property interface, the function can be made available for all platforms and not just the ones using DT. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: common: of_usb_get_maximum_speed to usb_get_maximum_speedHeikki Krogerus2015-09-271-1/+2
| | | | | | | | | By using the unified device property interface, the function can be made available for all platforms and not just the ones using DT. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: support for pinctrl state change during system sleepSekhar Nori2015-09-271-0/+5
| | | | | | | | | Add support for USB DRVVBUS pinctrl state change during suspend/resume. This helps is conserving power during system sleep. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: Add frame length adjustment quirkNikhil Badola2015-09-271-0/+34
| | | | | | | | | | Add adjust_frame_length_quirk for writing to fladj register which adjusts (micro)frame length to value provided by "snps,quirk-frame-length-adjustment" property thus avoiding USB 2.0 devices to time-out over a longer run Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: core: remove unnecessary dev_warn()Felipe Balbi2015-07-291-2/+0
| | | | | | | | | | | | | | | | When a SoC supports both PHY interfaces but doesn't define HSPHY in DT/pdata, we will get an unnecessary dev_warn() which can mislead users into thinking that they're missing something. Instead, let's just silently rely on a correct default. If the HW default is wrong, then HSPHY is required and USB won't work, this will be motivation enough for engineers to patch their way into a working setup. Reported-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: core: avoid NULL pointer dereferenceFelipe Balbi2015-07-061-2/+4
| | | | | | | | | | | | | | commit 3e10a2ce98d1 ("usb: dwc3: add hsphy_interface property") introduced a possible NULL pointer dereference because dwc->hsphy_interface can be NULL. In order to fix it, all we have to do is guard strncmp() against a NULL argument. Fixes: 3e10a2ce98d1 ("usb: dwc3: add hsphy_interface property") Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: add ULPI interface supportHeikki Krogerus2015-05-131-3/+31
| | | | | | | | | Registers DWC3's ULPI interface with the ULPI bus when it's available. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: add hsphy_interface propertyHeikki Krogerus2015-05-131-0/+20
| | | | | | | | | | | Platforms that have configured DWC_USB3_HSPHY_INTERFACE with value 3, i.e. UTMI+ and ULPI, need to inform the driver of the actual HSPHY interface type with the property. "utmi" if the interface is UTMI+ or "ulpi" if the interface is ULPI. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: setup phys earlierHeikki Krogerus2015-05-131-6/+2
| | | | | | | | | | | | | | | | | | | | This allows dwc3_phy_setup() to be more useful later. There is nothing preventing the PHY configuration registers from being programmed early. They do not loose their context in soft reset. There are however other PHY related operations that should be executed before the driver request handles to the PHYs, such as registering DWC3's ULPI interface, which can now be done in dwc3_phy_setup(). Also, if there ever was need for the two 100ms delays in dwc3_phy_setup() there isn't anymore. The PHYs are now reset after the PHY interfaces are setup. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: soft reset to it's own functionHeikki Krogerus2015-05-131-16/+30
| | | | | | | | So it can be called from other places later. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: cache hwparams earlierHeikki Krogerus2015-05-131-2/+1
| | | | | | | | So they are available when ULPI interface support is added. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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