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Intel Gemini Lake is essentially Broxton with different PCI IDs. Add these
new PCI IDs to the list of supported devices.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Device Support
- Add support for Ricoh RC5T619 PMIC to rn5t618
- Add support for PM8821 PMIC to qcom-pm8xxx
New Functionality:
- Add support for GPIO to lpc_ich
- Add support for GPADC to sun4i
- Add ability for rk808 to shutdown
Fix-ups:
- Simplify/strip unnecessary code; tps65218, palmas, tps65217
- Device Tree binding updates; tps65218, altera-a10sr
- Provide/export device ID info; tps65218, axp20x-i2c, hi655x-pmic,
fsl-imx25-tsadc, intel_soc_pmic_bxtwc
- Use MFD API instead of of_platform_populate(); tps65218
- Generalise name-space; pm8xxx
- Supply/edit regmap configuration; axp20x, cs47l24-tables, axp20x
- Enable compile testing; max77620, max77686, exynos-lpass,
abx500-core
- Coding style issues; wm8994-core, wm5102-tables
- Supply endian support; syscon
- Remove module support; ab3100-core, ab8500-debugfs, ab8500-gpadc,
abx500-core
Bug Fixes:
- Fix ordering issues; wm8994
- Fix dependencies (build-time/run-time); exynos_lpass, sun4i-gpadc
- Fix compiler warnings; sun4i-gpadc
- Fix leaks; mfd-core
- Fix page fault during module unload; tps65217"
* tag 'mfd-for-linus-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (49 commits)
mfd: tps65217: Support an interrupt pin as the system wakeup
mfd: tps65217: Make an interrupt handler simpler
mfd: tps65217: Update register interrupt mask bits instead of writing operation
mfd: tps65217: Specify the IRQ name
mfd: tps65217: Fix page fault on unloading modules
mfd: palmas: Remove redundant check in palmas_power_off
mfd: arizona: Disable IRQs during driver remove
mfd: pm8xxx: add support to pm8821
mfd: intel-lpss: Try to enable Memory-Write-Invalidate
mfd: rn5t618: Add Ricoh RC5T619 PMIC support
mfd: axp20x: Add address extension registers for AXP806 regmap
mfd: intel_soc_pmic_bxtwc: Fix a typo in MODULE_DEVICE_TABLE()
mfd: core: Fix device reference leak in mfd_clone_cell
mfd: bcm590xx: Simplify a test
mfd: sun4i-gpadc: Select regmap-irq
mfd: abx500-core: drop unused MODULE_ tags from non-modular code
mfd: ab8500: make sysctrl explicitly non-modular
mfd: ab8500-gpadc: Make it explicitly non-modular
mfd: ab8500-debugfs: Make it explicitly non-modular
mfd: ab8500-core: Make it explicitly non-modular
...
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Enable MWI mechanism if PCI bus master supports it.
It might be potential benefit in some cases. Documentation [1] says that
standard Memory Write might supply more current data than in the CPU modified
cache line and "trashing a line in the cache may trash some data that is more
current that in the memory line". This allows to avoid potential retries and
other performance degradation issues on the bus.
[1] PCI System Architecture, 4th edition, ISBN: 0-201-30974-2, pp.117-119.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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There are a few issues on Intel Kaby Lake PCH-H properties added by
commit a6a576b78e09 ("mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs"):
- Input clock of I2C controller on Intel Kaby Lake PCH-H is 120 MHz not
133 MHz. This was probably copy-paste error from Intel Broxton I2C
properties.
- There is no default I2C SDA hold time specified which is used when
ACPI doesn't provide it. I got information from Windows driver team
that Kaby Lake PCH-H can use the same configuration than Intel
Sunrisepoint PCH.
- Common HS-UART properties are not used.
Fix these by reusing the Sunrisepoint properties on Kaby Lake PCH-H.
Fixes: a6a576b78e09 ("mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs")
Reported-by: Xiang A Wang <xiang.a.wang@intel.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Default I2C device properties for Intel Broxton, especially SDA hold time
may not be enough on Intel Apollo Lake. These properties are used in case
we don't get timing parameters from ACPI.
The default SDA hold time for Broxton may fail with arbitration lost errors
on Apollo Lake:
i2c_designware i2c_designware.1: i2c_dw_handle_tx_abort: lost arbitration
Fix this by using different default device properties on Apollo Lake than
Broxton.
Reported-by: Paul Liu <paul.liu@canonical.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=156181
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Intel Kaby Lake PCH-H has the same LPSS than Intel Sunrisepoint. Add the new
IDs to the list of supported devices.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Since device_add_property_set() now always takes a copy of
the property_set, and also since the fwnode type is always
hard coded to be FWNODE_PDATA, there is no need for the
drivers to deliver the entire struct property_set. The
function can just create the instance of it on its own and
bind the properties from the drivers to it on the spot.
This renames device_add_property_set() to
device_add_properties(). The function now takes struct
property_entry as its parameter instead of struct
property_set.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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I2C host controller need to be configured properly in order to meet I2C
timings specified in the I2C protocol specification. Some Intel Broxton
based machines do not have this information in the ACPI namespace (or the
boot firmware does not support ACPI at all) so we use build-in device
properties instead.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Add PCI IDs for Intel Broxton B-Step platform, which have same
LPSS devices with A-Step.
Signed-off-by: Huiquan Zhong <huiquan.zhong@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
cked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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The HS-UART host controller driver needs to know certain properties like
width of the register set if it cannot get that information from ACPI or
DT. In order to support non-ACPI systems we pass this information to the
driver via device properties.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Intel Skylake the LPSS I2C pad circuit has internal delays that require
programming non-zero SDA hold time for the I2C host controller. If this is
not done communication to slave devices may fail with arbitration lost
errors like the one seen below taken from Lenovo Yoga 900:
i2c_hid i2c-SYNA2B29:00: Fetching the HID descriptor
i2c_hid i2c-SYNA2B29:00: __i2c_hid_command: cmd=20 00
i2c_designware i2c_designware.1: i2c_dw_handle_tx_abort: lost arbitration
To fix this we follow what the Windows driver is doing and pass the default
SDA hold time of 230 ns to all Intel Skylake host controllers. This still
allows the platform to override these values by passing special ACPI
methods SSCN and FMCN.
Reported-by: Kevin Fenzi <kevin@scrye.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Intel Broxton has the same LPSS block than Intel Sunrisepoint so add
Broxton PCI IDs to the list.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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The new coming Intel platforms such as Skylake will contain Sunrisepoint PCH.
The main difference to the previous platforms is that the LPSS devices are
compound devices where usually main (SPI, HSUART, or I2C) and DMA IPs are
present.
This patch brings the driver for such devices found on Sunrisepoint PCH.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
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