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path: root/drivers/gpu/drm/tegra/dc.h
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* drm/tegra: sor: Add HDMI supportThierry Reding2015-08-131-0/+4
| | | | | | | | | The SOR1 introduced on Tegra210 supports HDMI 2.0 and DisplayPort. Add HDMI support and name the debugfs node after the type of SOR. The SOR introduced with Tegra124 is known simply as "sor", whereas the additional SOR found on Tegra210 is known as "sor1". Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Rename BASE_COLOR_SIZE* fieldsThierry Reding2015-08-131-0/+9
| | | | | | Use an underscore to separate the prefix from the color size suffix. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Rename register for consistencyThierry Reding2015-08-131-3/+3
| | | | | | | The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the TRM. Modify the driver to use the same naming for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Implement CRC debugfs interfaceThierry Reding2015-08-131-0/+5
| | | | Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc: Implement hardware VBLANK counterThierry Reding2015-04-021-4/+3
| | | | | | | | The display controller on Tegra can use syncpoints to count VBLANK events. syncpoints are 32-bit unsigned integers, so well suited as VBLANK counters. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Implement more tiling modesThierry Reding2014-08-041-0/+5
| | | | | | | | | Tegra124 supports a block-linear mode in addition to the regular pitch linear and tiled modes. Add support for these by moving the internal representation into a structure rather than a simple flag. Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Add hardware cursor supportThierry Reding2014-06-051-3/+27
| | | | | | | | Enable hardware cursor support on Tegra124. Earlier generations support the hardware cursor to some degree as well, but not in a way that can be generically exposed. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dc - Rename INVERT_V to V_DIRECTIONThierry Reding2014-06-051-1/+2
| | | | | | | V_DIRECTION is the name of the field in the documentation, so use that for consistency. Also add the H_DIRECTION field for completeness. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Add eDP supportThierry Reding2014-04-041-0/+1
| | | | | | | Add support for eDP functionality found on Tegra124 and later SoCs. Only fast link training is currently supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Relocate some output-specific codeThierry Reding2013-12-201-0/+2
| | | | | | | | Some of the code in the CRTC's mode setting code is specific to the RGB output or needs to be called slightly differently depending on the type of output. Push that code down into the output drivers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Add Tegra124 DC supportThierry Reding2013-12-201-0/+5
| | | | | | | | Tegra124 and later support interlacing, but the driver doesn't support it yet. Make sure interlacing stays disabled on hardware that supports it. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Add DSI supportThierry Reding2013-12-201-0/+2
| | | | | | | | | | | This commit adds support for both DSI outputs found on Tegra. Only very minimal functionality is implemented, so advanced features like ganged mode won't work. Due to the lack of other test hardware, some sections of the driver are hardcoded to work with Dalmore. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Support bottom-up buffer objectsThierry Reding2013-10-311-0/+1
| | | | | | | | | The gr3d engine renders images bottom-up. Allow buffers that are used for 3D content to be marked as such and implement support in the display controller to present them properly. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Add support for tiled buffer objectsThierry Reding2013-10-311-0/+4
| | | | | | | | | The gr2d and gr3d engines work more efficiently on buffers with a tiled memory layout. Allow created buffers to be marked as tiled so that the display controller can scan them out properly. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Move driver to DRM treeThierry Reding2013-10-311-0/+400
| | | | | | | In order to make subsystem-wide changes easier, move the Tegra DRM driver back into the DRM tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Move drm to live under host1xTerje Bergstrom2013-04-221-400/+0
| | | | | | | | | | | Make drm part of host1x driver. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Erik Faye-Lund <kusmabite@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
* drm/tegra: Implement page-flipping supportThierry Reding2013-02-221-0/+2
| | | | | | | All the necessary support bits like .mode_set_base() and VBLANK are now available, so page-flipping case easily be implemented on top. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
* drm/tegra: Add plane supportThierry Reding2013-02-221-1/+11
| | | | | | | | | | Add support for the B and C planes which support RGB and YUV pixel formats and can be used as overlays or hardware cursor. Currently 32-bit XRGB as well as UYVY, YUV420 and YUV422 pixel formats are advertised. Other formats should be easy to add but these are the most common ones and should cover the majority of use-cases. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
* drm: Add NVIDIA Tegra20 supportThierry Reding2012-11-201-0/+388
This commit adds a KMS driver for the Tegra20 SoC. This includes basic support for host1x and the two display controllers found on the Tegra20 SoC. Each display controller can drive a separate RGB/LVDS output. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Zhang <markz@nvidia.com> Reviewed-by: Mark Zhang <markz@nvidia.com> Tested-by: Mark Zhang <markz@nvidia.com> Tested-and-acked-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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