summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd
Commit message (Collapse)AuthorAgeFilesLines
...
| * | drm/amdgpu: move PD/PT bos on LRU againHuang Rui2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new bulk moving functionality is ready, the overhead of moving PD/PT bos to LRU is fixed. So move them on LRU again. Signed-off-by: Huang Rui <ray.huang@amd.com> Tested-by: Mike Lothian <mike@fireburn.co.uk> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use bulk moves for efficient VM LRU handling (v6)Huang Rui2018-08-273-23/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I continue to work for bulk moving that based on the proposal by Christian. Background: amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of them on the end of LRU list one by one. Thus, that cause so many BOs moved to the end of the LRU, and impact performance seriously. Then Christian provided a workaround to not move PD/PT BOs on LRU with below patch: Commit 0bbf32026cf5ba41e9922b30e26e1bed1ecd38ae ("drm/amdgpu: band aid validating VM PTs") However, the final solution should bulk move all PD/PT and PerVM BOs on the LRU instead of one by one. Whenever amdgpu_vm_validate_pt_bos() is called and we have BOs which need to be validated we move all BOs together to the end of the LRU without dropping the lock for the LRU. While doing so we note the beginning and end of this block in the LRU list. Now when amdgpu_vm_validate_pt_bos() is called and we don't have anything to do, we don't move every BO one by one, but instead cut the LRU list into pieces so that we bulk move everything to the end in just one operation. Test data: +--------------+-----------------+-----------+---------------------------------------+ | |The Talos |Clpeak(OCL)|BusSpeedReadback(OCL) | | |Principle(Vulkan)| | | +------------------------------------------------------------------------------------+ | | | |0.319 ms(1k) 0.314 ms(2K) 0.308 ms(4K) | | Original | 147.7 FPS | 76.86 us |0.307 ms(8K) 0.310 ms(16K) | +------------------------------------------------------------------------------------+ | Orignial + WA| | |0.254 ms(1K) 0.241 ms(2K) | |(don't move | 162.1 FPS | 42.15 us |0.230 ms(4K) 0.223 ms(8K) 0.204 ms(16K)| |PT BOs on LRU)| | | | +------------------------------------------------------------------------------------+ | Bulk move | 163.1 FPS | 40.52 us |0.244 ms(1K) 0.252 ms(2K) 0.213 ms(4K) | | | | |0.214 ms(8K) 0.225 ms(16K) | +--------------+-----------------+-----------+---------------------------------------+ After test them with above three benchmarks include vulkan and opencl. We can see the visible improvement than original, and even better than original with workaround. v2: move all BOs include idle, relocated, and moved list to the end of LRU and put them together. v3: remove unused parameter and use list_for_each_entry instead of the one with save entry. v4: move the amdgpu_vm_move_to_lru_tail after command submission, at that time, all bo will be back on idle list. v5: remove amdgpu_vm_move_to_lru_tail_by_list(), use bulk_moveable instread of validated, and move ttm_bo_bulk_move_lru_tail() also into amdgpu_vm_move_to_lru_tail(). v6: clean up and fix return value. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Tested-by: Mike Lothian <mike@fireburn.co.uk> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/ttm: revise ttm_bo_move_to_lru_tail to support bulk movesChristian König2018-08-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When move a BO to the end of LRU, it need remember the BO positions. Make sure all moved bo in between "first" and "last". And they will be bulk moving together. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Tested-by: Mike Lothian <mike@fireburn.co.uk> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add amdgpu_gmc_pd_addr helperChristian König2018-08-279-23/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper to get the root PD address and remove the workarounds from the GMC9 code for that. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: remove gart.table_addrChristian König2018-08-279-25/+24
| | | | | | | | | | | | | | | | | | | | | | | | We can easily figure out the address on the fly. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: rename gart.robj into gart.boChristian König2018-08-276-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sed -i "s/gart.robj/gart.bo/" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/gart.robj/gart.bo/" drivers/gpu/drm/amd/amdgpu/*.h Just cleaning up radeon leftovers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: move setting the GART addr into TTMChristian König2018-08-272-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move setting the GART addr for window based copies into the TTM code who uses it. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: cleanup VM handling in the CS a bitChristian König2018-08-271-86/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper function for getting the root PD addr and cleanup join the two VM related functions and cleanup the function name. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: validate the VM root PD from the VM codeChristian König2018-08-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Preparation for following changes. This validates the root PD twice, but the overhead of that should be minimal. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: cleanup GPU recovery check a bit (v2)Christian König2018-08-278-22/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check if we should call the function instead of providing the forced flag. v2: rebase on KFD changes (Alex) Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: amdgpu_kiq_reg_write_reg_wait() can be statickbuild test robot2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | Fixes: d790449835e6 ("drm/amdgpu: use kiq to do invalidate tlb") Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/display: add support for LVDS (v5)Alex Deucher2018-08-2710-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for LVDS displays. v2: add support for spread spectrum, sink detect v3: clean up enable_lvds_output v4: fix up link_detect v5: remove assert on 888 format Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105880 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Don't use kiq in gpu resetEmily Deng2018-08-271-11/+4
| | | | | | | | | | | | | | | | | | | | | | | | When in gpu reset, don't use kiq, it will generate more TDR. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: indent an if statementDan Carpenter2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The if statement isn't indented and it makes static checkers complain. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: fix a compile warningWen Yang2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix comile warning like, CC [M] drivers/gpu/drm/i915/gvt/execlist.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o CC [M] drivers/gpu/drm/radeon/btc_dpm.o CC [M] drivers/isdn/hisax/avm_a1p.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.o drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function ‘dcn10_update_mpcc’: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1903:9: warning: missing braces around initializer [-Wmissing-braces] struct mpcc_blnd_cfg blnd_cfg = {0}; ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1903:9: warning: (near initialization for ‘blnd_cfg.black_color’) [-Wmissing-braces] Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Reviewed-by: Jiang Biao <jiang.biao2@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sriov: Only sriov runtime support use kiqEmily Deng2018-08-271-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | For sriov, don't use kiq in exclusive mode, as don't know how long time it will take, some times it will occur exclusive timeout. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix sdma doorbell range settingEvan Quan2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the old doorbell range setting until the driver is able to support more sdma queues. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Fix compile warningRex Zhu2018-08-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function ‘gfx_v9_0_check_fw_write_wait’: warning: enumeration value ‘CHIP_TAHITI’ not handled in switch [-Wswitch] Always add default case in case there is no match Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: rework ctx entity creationChristian König2018-08-273-167/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a fixed number of entities for each hardware IP. The number of compute entities is reduced to four, SDMA keeps it two entities and all other engines just expose one entity. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: cleanup HW_IP queryChristian König2018-08-271-94/+110
| | | | | | | | | | | | | | | | | | | | | | | | Move the code into a separate function. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: remove fulll access for suspend phase1Yintian Tao2018-08-271-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for gpu full access for suspend phase1 because under virtualization there is no hw register access for dce block. Signed-off-by: Yintian Tao <yttao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use kiq to do invalidate tlbEmily Deng2018-08-273-10/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid the tlb flush not interrupted by world switch, use kiq and one command to do tlb invalidate. v2: Refine the invalidate lock position. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-and-Tested-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Remove the sriov checking and add firmware checkingEmily Deng2018-08-272-1/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unify bare metal and sriov, and add firmware checking for reg write and reg wait unify command. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: implement DPMS DTN test v2Jun Lei2018-08-275-2/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Existing DTN infrastructure in driver is hacky. It uses implicit log names, and also incorrect escape ID. [how] - Implement using generic DTN escape ID. - Move file logging functionality from driver to to script; driver now outputs to string/buffer - Move HWSS debug functionality to separate c file - Add debug functionalty for per-block logging as CSV - Add pretty print in python Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: move edp fast boot optimization flag to streamAnthony Koo2018-08-274-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] During S4/S3 stress test it is possible to resume from S4 without calling mode set on eDP, meaning high level optimization flag is not reset. If this is followed by an S3 resume call, driver will see optimization flag is set and consume it and think backend is powered on when in fact it is not. This results in PHY being off in sequence where S4->Resume->S3->Resume->ApplyOpt->black screen. [How] Move optimization flag to stream instead of a DC flag. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Combine dce80 and dce100 i2c hw functionsDavid Francis2018-08-271-197/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There are two versions of the hw function pointers: one for dce80 and one for all other versions. These paired functions are nearly identical. dce80 and dce100 should not require different i2c access functions. [How] Combine each pair of functions into a single function. Mostly the new functions are based on the dce100 versions as those versions are newer, support more features, and were more maintained. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Define registers for dcn10Nikola Cornij2018-08-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Define register for dcn10 for future changes Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Program csc matrix as part of stream updateSivapiriyanKumarasamy2018-08-272-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add csc_transform struct to dc_stream_update, and program if set when updating streams Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Create new i2c resourceDavid Francis2018-08-2718-30/+2452
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] I2C code did not match dc resource model and was generally unpleasant [How] Move code into new svelte dce_i2c files, replacing various i2c objects with two structs: dce_i2c_sw and dce_i2c_hw. Fully split sw and hw code paths. Remove all redundant declarations. Use address lists to distinguish between versions. Change dce80 code to newer register access macros. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Do not evict VRAM on APUs with disabled HIBERNATEPaul Menzel2018-08-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve commit d796d844 (drm/radeon/kms: make hibernate work on IGPs) to only migrate VRAM objects if the Linux kernel is actually built with support for hibernation (suspend to disk). The better solution is to get the information, if this is suspend or hibernate, from `amdgpu_device_suspend()`, but that’s more involved, so apply the simple solution first. Link: https://bugs.freedesktop.org/show_bug.cgi?id=107277 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add status checking after fw is loadedHuang Rui2018-08-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | The status field must be 0 after FW is loaded. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix VM size reporting on RavenChristian König2018-08-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raven doesn't have an VCE block and so also no buggy VCE firmware. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Set clock ungate state when suspend/finiRex Zhu2018-08-271-51/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | After set power ungate state, set clock ungate state before when suspend or fini. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Set power ungate state when suspend/finiRex Zhu2018-08-273-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unify to set power ungate state at the begin of suspend/fini. Remove the workaround code for gfx off feature in amdgpu_device.c. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Refine function name and function argsRex Zhu2018-08-271-20/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are no any logical changes here. 1. change function names: amdgpu_device_ip_late_set_pg/cg_state to amdgpu_device_set_pg/cg_state. 2. add a function argument cg/pg_state, so we can enable/disable cg/pg through those functions Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Program gamut remap as part of stream updateSivapiriyanKumarasamy2018-08-272-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gamut remap to dc_stream_update struct, and program if set when updating streams. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: HDR dynamic meta should be treated as stream updateKrunoslav Kovac2018-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Recently we fixed HDR static meta using AFMT registers to be treated as fast stream update. Dynamic meta is still being treated as (full) surface update because it touches HUBP and it travels with pipe data. Here we change it to be (fast) stream update. Note, originally we also wanted to redesign here a bit, but without OS level support for true dynamic meta, it's left the same. We are simply using HW that can do dynamic meta to send HDR static meta, I still prefer keeping it in one static meta type then defining dynamic meta types to hold the same info. Once we know how OS interfaces look like, we can do proper design. [How] Move dyn meta update from update_hubp_dpp to commit_planes_do_stream_update Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Handle HDR meta update as fast updateKrunoslav Kovac2018-08-271-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Vesa DPMS tool sends different HDR meta in OS flips without changing output parameters. We don't properly update HDR info frame: - we label HDR meta update as fast update - when updating HW info frame, we only do it if full update [How] It should still be fast update, so when doing HW infoframe update, do it always no matter the update type. Also, don't request passive flip for HDR meta update only without output transfer function or color space changed. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Program vsc_infopacket in commit_planes_for_streamAlvin lee2018-08-272-1/+3
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alvin lee <alvin.lee3@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Enable Stereo in Dal3Alvin lee2018-08-278-38/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - program infoframe for Stereo - program stereo flip control registers properly v2: Add missing license headers Signed-off-by: Alvin lee <alvin.lee3@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Program vline interrupt on FAST updateSivapiriyanKumarasamy2018-08-271-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: decouple front and backend pgm using dpms_off as backend ↵Samson Tam2018-08-275-82/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | enable flag Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: add config for sending VSIFAnthony Koo2018-08-273-1/+5
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Don't force UPDATE_TYPE_FULL if stream_update has ↵Harry Wentland2018-08-271-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hdr_static_metadata This was missed when pushing public patch for 3e3a40b03847 (drm/amd/display: Updated HDR Static Metadata to directly take info packet raw) This is currently no problem yet since we're not doing HDR on Linux yet. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Correct rounding calcs in mod_freesync_is_valid_rangeAnthony Koo2018-08-271-5/+34
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: refactor vupdate interrupt registrationAnthony Koo2018-08-271-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only need to register once OS calls the interrupt control. Also, if we are entering static screen mode, disable after ramping is done. Disable shall be done via timer of 2 seconds regardless of ramping complete or not, just to simplify. Also, ramp to mid instead of min, due to better flicker performance... Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: fix LFC tearing at top of screenAnthony Koo2018-08-271-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tearing occurred because new VTOTAL MIN/MAX was being programmed too early. The flip can happen within the VUPDATE high region, and the new min/max would take effect immediately. But this means that frame is not variable anymore, and tearing would occur when the flip actually happens. The fixed insert duration should be programmed on the first VUPDATE interrupt instead. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add back code to allow for rounding errorAnthony Koo2018-08-271-1/+12
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Fix bug that causes black screenAnthony Koo2018-08-271-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ignore MSA bit on DP display is usually set during SetTimings, but there was a case where the module thought refresh rate was not valid and ignore MSA bit was not set. Later, a valid refresh rate range was requested but since ignore MSA bit not set, it caused black screen. Issue if with how the module checked for VRR support. Fix up that logic. DM should call new valid_range function to determine if timing is supported. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Fix bug where refresh rate becomes fixedAnthony Koo2018-08-272-20/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This issue occurs if refresh rate range is very small and lfc is not used. When frame spikes occur, refresh rate becomes fixed and will not restore properly Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
OpenPOWER on IntegriCloud