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| * | drm/amd/powerplay: update OD to take voltage value instead of offsetEvan Quan2018-09-195-41/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the latest SMC fw, we are able to get the voltage value for specific frequency point. So, we update the OD relates to take absolute voltage instead of offset. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: update OD feature judgementEvan Quan2018-09-192-26/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update the conditions to judge whether an OD feature should be supported on vega20. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix unknown vram mem type for vega20Hawking Zhang2018-09-191-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vega20 should use umc_info v3_3 instead of v3_1. There are serveral versions of umc_info for vega series. Compared to various versions of these structures, vram_info strucure is unified for vega series. The patch switch to query mem_type from vram_info structure for all the vega series dGPU. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: update vram_info structure in atomfirmware.hHawking Zhang2018-09-192-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | atomfirmware has structure changes in varm_info. Updated it to the latest one. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use processed values for countingA. Wilcox2018-09-192-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adev->gfx.rlc has the values from rlc_hdr already processed by le32_to_cpu. Using the rlc_hdr values on big-endian machines causes a kernel Oops due to writing well outside of the array (0x24000000 instead of 0x24). Signed-off-by: A. Wilcox <AWilcox@Wilcox-Tech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/amdgpu: Avoid fault when allocating an empty buffer objectTom St Denis2018-09-191-1/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: drop size checkChristian König2018-09-191-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | We no don't allocate zero sized kernel BOs any longer. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: don't allocate zero sized kernel BOsChristian König2018-09-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Just free the BO if the size should be zero. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: stop crashing on GDS/GWS/OA evictionChristian König2018-09-191-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Simply ignore any copying here. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add GDS, GWS and OA debugfs filesChristian König2018-09-191-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Additional to the existing files for VRAM and GTT. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix parameter documentation for amdgpu_vm_free_ptsChristian König2018-09-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | The function was modified without updating the documentation. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add amdgpu_vm_entries_mask v2Christian König2018-09-191-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can't get the mask for the root directory from the number of entries. So add a new function to avoid that problem. v2: fix typo in mask Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Drop amdgpu_dm_prev_state structLeo Li2018-09-141-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] It's not being used [How] Nuke it Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Drop amdgpu_display_manager.dal memberLeo Li2018-09-142-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] It's not being used anymore. [How] Nuke it Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: add query HPD interface.Chiawen Huang2018-09-142-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] current dc_link_detect function is not only detection but also update some link data. [How] added a pure get HPD state function. Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: dc 3.1.66Tony Cheng2018-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: add aux i2c event log.Chiawen Huang2018-09-143-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] support i2c transition event log [How] refined aux REQ and REP events in aux flow. commented REQ and REP events in i2c flow. note: i2c event log is currently commented out. more work is required to find an portocol parser to and generate event for the parser Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: stop using switch for different CS revisionsDmytro Laktyushkin2018-09-145-167/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock sources currently have support for asic specific function pointers. But actual separation into functions was never performed, leaving us with giant functions that rely on switch. This change creates separate functions, removing switch use. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Fix 3D stereo issues.Charlene Liu2018-09-145-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were not providing the correct pixel clocks to DML for marks calculation. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: revert "stop using gart_start as offset for the GTT domain"Christian König2018-09-142-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turned out the commit is incomplete and since we remove using the AGP mapping from the GTT manager it is also not necessary any more. This reverts commit 22d8bfafcc12dfa17b91d2e8ae4e1898e782003a. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix mask in GART location calculationChristian König2018-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to mask the lower bits not the upper one. Fixes: ec210e3226dc0 drm/amdgpu: put GART away from VRAM v2 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/display: return proper error codes in dmAlex Deucher2018-09-141-4/+4
| | | | | | | | | | | | | | | | | | | | | Replace -1 with proper error codes. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: simplify Raven, Raven2, and Picasso handlingAlex Deucher2018-09-1415-112/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Treat them all as Raven rather than adding a new picasso asic type. This simplifies a lot of code and also handles the case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu fw handling for picasso. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/soc15: clean up picasso supportAlex Deucher2018-09-141-17/+0
| | | | | | | | | | | | | | | | | | | | | It's the same as raven so remove the duplicate case. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Add DMCU to firmware query interfaceDavid Francis2018-09-141-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | DMCU firmware version can be read using the AMDGPU_INFO ioctl or the amdgpu_firmware_info debugfs entry Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DMCU firmware versionDavid Francis2018-09-142-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Read the version number from the common firmware header and store it in the dm struct Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Style fixes to PRIME code documentationVijetha Malkai2018-09-141-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Use consistent capitalization in the description of function arguments * Define and consistently use the BO acronym for buffer objects * Some minor wording improvements Signed-off-by: Vijetha Malkai <vijetha.malkai@amd.com> [ Michel Dänzer: Made commit log more specific ] Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_holeMichel Dänzer2018-09-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The entries were only initialized once in amdgpu_sa_bo_new. If a fence wasn't signalled yet in the first amdgpu_sa_bo_next_hole call, but then got signalled before a later amdgpu_sa_bo_next_hole call, it could destroy the fence but leave its pointer in the array, resulting in use-after-free in amdgpu_sa_bo_new. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: set CG flags for raven2 (v2)Huang Rui2018-09-141-20/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raven2 does not enable all of the CG flags that raven1 does. v2: rebase (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: disable raven2 force dpm level support (v2)Evan Quan2018-09-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not supported yet. v2: rebase (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: round up the Mhz convertion (v2)Evan Quan2018-09-141-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the clock value there may be like 29999 10Khz. v2: rebase (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatibleEvan Quan2018-09-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Check the raven2 version number as well. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add DC config flag for Raven2 (v2)Bhawanpreet Lakha2018-09-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DRM_AMD_DC_DCN1_01 config flag for Raven2 v2: Make DC select DRM_AMD_DC_DCN1_01 (Alex) Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Add Raven2 definitions in dcBhawanpreet Lakha2018-09-149-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Raven2 definitions in the dc code Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix the VM fault while write at the top of the invisible vramHuang Rui2018-09-142-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raven2 has a HW issue that it is unable to use the vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the workaround that increase system aperture high address to get rid of the VM fault and hardware hang. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx9: add raven2 golden settingFeifei Xu2018-09-141-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | Golden register settings from the hw team. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx9: add support for raven2 gfx firmwareFeifei Xu2018-09-141-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | use raven2 gfx firmware. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma4: Add raven2 golden settingFeifei Xu2018-09-141-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | Golden register settings from the hw team. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma4: specify raven2 firmware.Feifei Xu2018-09-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | use raven2 sdma firmware. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add psp support for raven2Likun Gao2018-09-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Modified for using raven2_asd.bin to replace raven_asd.bin for raven2 Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add raven2 vcn firmware supportFeifei Xu2018-09-141-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | Specify raven2 vcn firmware on amdgpu_vce_sw_init. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add raven2 to gpu_info firmwareFeifei Xu2018-09-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add gpu_info firmware for raven2. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: set external rev id for raven2Alex Deucher2018-09-141-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | It's different from raven1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: move get_rev_id at first before load gpu_info firmwareHuang Rui2018-09-141-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rev id is used for identifying Raven2 series of chips. So we would better to initialize it at first. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use IP presence to free uvd and vce handlesAlex Deucher2018-09-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Rather than checking the asic type, check whether the UVD or VCE IP blocks exist. This way we don't have to update the check with new asics that use VCN. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable gfxoff in non-sriov and stutter mode by defaultKenneth Feng2018-09-142-2/+4
| | | | | | | | | | | | | | | | | | | | | enable gfxoff in non-sriov and stutter mode by default Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add new raven series deviceHuang Rui2018-09-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to add new pci device for raven series. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add ip blocks for picasso (v2)Huang Rui2018-09-141-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCO IPs. V2: enable VCN as well Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable vcn powergating for PCOKenneth Feng2018-09-141-1/+3
| | | | | | | | | | | | | | | | | | | | | enable vcn pg Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable mmhub power gatingKenneth Feng2018-09-144-223/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove some functions due to the design change. All the mmhub power gating sequence is moved to smu fw.Driver sends the message to enable mmhub powergating.We can also skip the fw version check since the old fw version is in a very early stage and we don't use that fw for release. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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