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* | | drm/amdkfd: reflect atomic support in IO link propertiesEric Huang2018-09-263-12/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the flags of properties according to Asic type and pcie capabilities. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Add warning message for INT SW fallback.Andrey Grodzovsky2018-09-261-0/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | Revert "drm/amdgpu: remove fence fallback"Andrey Grodzovsky2018-09-263-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55. This commit breaks KCQ IB test and S3 on Polaris 11. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:No action when VCN PG state is unchangedJames Zhu2018-09-262-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When VCN PG state is unchanged, it is unnecessary to reset power gate state Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: remove redundant null pointer check before kfreezhong jiang2018-09-261-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | kfree has taken the null pointer into account. hence it is safe to remove the redundant null pointer check before kfree. Signed-off-by: zhong jiang <zhongjiang@huawei.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: print smc feature mask in debugfs amdgpu_pm_infoAlex Deucher2018-09-261-0/+5
| | | | | | | | | | | | | | | | | | | | | Print the enabled smc feature mask in amdgpu_pm_info for debugging. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega20Alex Deucher2018-09-261-0/+5
| | | | | | | | | | | | | | | | | | | | | So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega12Alex Deucher2018-09-261-1/+5
| | | | | | | | | | | | | | | | | | | | | So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega10Alex Deucher2018-09-263-4/+11
| | | | | | | | | | | | | | | | | | | | | So we can query what features are enabled for debugging. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: add new AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK sensorAlex Deucher2018-09-261-0/+1
| | | | | | | | | | | | | | | | | | | | | For getting the 64 bit enabled smc feature mask from vega parts. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: add smu smc_table_manager callback for vega20Alex Deucher2018-09-263-24/+34
| | | | | | | | | | | | | | | | | | | | | For consistency with other asics. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: add smu smc_table_manager callback for vega12Alex Deucher2018-09-263-12/+22
| | | | | | | | | | | | | | | | | | | | | For consistency with other asics. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: Move vega10_enable_smc_featuresAlex Deucher2018-09-266-12/+15
| | | | | | | | | | | | | | | | | | | | | to vega10_smumgr.c. For consistency with other vega parts. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: add get_argument callback for vega20Alex Deucher2018-09-264-32/+15
| | | | | | | | | | | | | | | | | | | | | For consistency with other vega parts. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: Raise dispclk value for dce120 by 15%Nicholas Kazlauskas2018-09-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The DISPCLK value was previously requested to be 15% higher for all ASICs that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and the dce110 set bandwidth codepath this was removed for power saving considerations. That change caused display corruption under certain hardware configurations with Vega10. [How] The 15% DISPCLK increase is brought back but only on dce110 for now. This is should be a temporary workaround until the root cause is sorted out for why this occurs on Vega (or other ASICs, if reported). Tested-by: Nick Sarnie <sarnex@gentoo.org> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: fix gamma not being appliedSivapiriyanKumarasamy2018-09-261-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] Previously night light forced a full update by applying a transfer function update regardless of if it was changed. This logic was removed, Now gamma surface updates are only applied when there is also a plane info update, this does not work in cases such as using the night light slider. [HOW] When moving the night light slider we will perform a full update if the gamma has changed and there is a surface, even when the surface has not changed. Also get stream updates in setgamma prior to update planes and stream. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: Remove mst_hotplug_workLeo Li2018-09-262-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The work struct's schedule call was removed a while ago, making this useless. [How] Remove it. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: Guard against null stream dereference in do flipNicholas Kazlauskas2018-09-261-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] During suspend under some hardware configurations can result in a series of atomic commits with a NULL stream status - which causes a NULL pointer dereference. This should be guarded. [How] Exit early from the function - if we can't access the stream then there isn't anything that can be done here. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: Stereo 3D support in VSCEric Bernstein2018-09-261-4/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Need to add strere 3D information in VSC [How] Update mod_build_vsc_infopacket with stereo info Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: dc 3.1.67Tony Cheng2018-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: program v_update and v_ready with proper fieldSu Sung Chung2018-09-263-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] There are two different variables used to calculate v_update and v_ready, one for validation and the other for performance parameter calculation. Before the variable for validation was used which caused underflow on 1080edp with vsr enabled [HOW] program v_update and v_ready with the variables for performance parameter calculation Signed-off-by: Su Sung Chung <su.chung@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: Add color bit info to freesync infoframeSivapiriyanKumarasamy2018-09-264-21/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parse the native color bit and send it to freesync module for future use Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: add pp_smu NULL pointer checkCharlene Liu2018-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | add pp_smu NULL ptr check Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: use proper pipe_ctx indexSamson Tam2018-09-261-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use link->link_index as index to pipe_ctx[] to get proper link information instead of using index 0 to avoid potential miss matches. Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: Refactor FPGA-specific link setupNikola Cornij2018-09-263-40/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FPGA doesn't program backend, so we don't need certain link settings (audio stream for example). Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/pp: Return error immediately if load firmware failedRex Zhu2018-09-261-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | this can avoid hard hang and be useful for debug. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/pp: Honour DC's clock limits on RvRex Zhu2018-09-261-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | Honour display's request for min engine clock/memory clock. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/dc: Trigger set power state task when display configuration changesRex Zhu2018-09-261-0/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "drm/amd/display: Remove call to amdgpu_pm_compute_clocks" This reverts commit dcd473770e86517543691bdb227103d6c781cd0a. when display configuration changes, dc need to update the changes to powerplay, also need to trigger a power state task. amdgpu_pm_compute_clocks is the interface to set power state task either dpm enabled or powerplay enabled Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | BackMerge v4.19-rc5 into drm-nextDave Airlie2018-09-2712-19/+50
|\| | | | | | | | | | | Sean Paul requested an -rc5 backmerge from some sun4i fixes. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/amdkfd: Fix ATS capablity was not reported correctly on some APUsYong Zhao2018-09-203-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Because CRAT_CU_FLAGS_IOMMU_PRESENT was not set in some BIOS crat, we need to workaround this. For future compatibility, we also overwrite the bit in capability according to the value of needs_iommu_device. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9Yong Zhao2018-09-205-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CWSR fails on Raven if the control stack is MTYPE_UC, which is used for regular GART mappings. As a workaround we map it using MTYPE_NC. The MEC firmware expects the control stack at one page offset from the start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU added a memory allocation flag just for this purpose. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Fix SDMA HQD destroy error on gfx_v7Amber Lin2018-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | A wrong register bit was examinated for checking SDMA status so it reports false failures. This typo only appears on gfx_v7. gfx_v8 checks the correct bit. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: add new polaris pci idAlex Deucher2018-09-192-6/+9
| | | | | | | | | | | | | | | | Add new pci id. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * drm/amdgpu: fix error handling in amdgpu_cs_user_fence_chunkChristian König2018-09-111-8/+15
| | | | | | | | | | | | | | | | Slowly leaking memory one page at a time :) Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: move PSP init prior to IH in gpu resetEmily Deng2018-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | since we use PSP to program IH regs now Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Fix SDMA hang in prt mode v2Tao Zhou2018-09-101-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix SDMA hang in prt mode, clear XNACK_WATERMARK in reg SDMA0_UTCL1_WATERMK to avoid the issue Affected ASICs: VEGA10 VEGA12 RV1 RV2 v2: add reg clear for SDMA1 Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Tested-by: Yukun Li <yukun1.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: fix amdgpu_mn_unlock() in the CS error pathChristian König2018-09-101-1/+1
| | | | | | | | | | | | | | | | Avoid unlocking a lock we never locked. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2018-09-21260-7796/+81060
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next This is a new pull for drm-next on top of last weeks with the following changes: - Fixed 64 bit divide - Fixed vram type on vega20 - Misc vega20 fixes - Misc DC fixes - Fix GDS/GWS/OA domain handling Previous changes from last week: amdgpu/kfd: - Picasso (new APU) support - Raven2 (new APU) support - Vega20 enablement - ACP powergating improvements - Add ABGR/XBGR display support - VCN JPEG engine support - Initial xGMI support - Use load balancing for engine scheduling - Lots of new documentation - Rework and clean up i2c and aux handling in DC - Add DP YCbCr 4:2:0 support in DC - Add DMCU firmware loading for Raven (used for ABM and PSR) - New debugfs features in DC - LVDS support in DC - Implement wave kill for gfx/compute (light weight reset for shaders) - Use AGP aperture to avoid gart mappings when possible - GPUVM performance improvements - Bulk moves for more efficient GPUVM LRU handling - Merge amdgpu and amdkfd into one module - Enable gfxoff and stutter mode on Raven - Misc cleanups Scheduler: - Load balancing support - Bug fixes ttm: - Bulk move functionality - Bug fixes radeon: - Misc cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180920150438.12693-1-alexander.deucher@amd.com
| * | drm/amdgpu: Exclude MM engines for vega20 virtual deviceFrank Min2018-09-191-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Temporary disable UVD/VCE block if is virtual device Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add vega20 sriov capability detectionFrank Min2018-09-191-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sriov capability detection for vega20, then can check if device is virtual device. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: move reserving GDS/GWS/OA into common codeChristian König2018-09-194-57/+18
| | | | | | | | | | | | | | | | | | | | | | | | We don't need that in the per ASIC code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: initialize GDS/GWS/OA domains even when they are zero sizedChristian König2018-09-191-30/+18
| | | | | | | | | | | | | | | | | | | | | | | | Stops crashing on SI. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix up GDS/GWS/OA shiftingChristian König2018-09-199-71/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | That only worked by pure coincident. Completely remove the shifting and always apply correct PAGE_SHIFT. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix shadow BO restoringChristian König2018-09-193-120/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Don't grab the reservation lock any more and simplify the handling quite a bit. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: always recover VRAM during GPU recoveryChristian König2018-09-191-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | It shouldn't add much overhead and we should make sure that critical VRAM content is always restored. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: shadow BOs don't need any alignmentChristian König2018-09-191-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | They aren't directly used by the hardware. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: always enable shadow BOs v2Christian König2018-09-191-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even when GPU recovery is disabled we could run into a manually triggered recovery. v2: keep accidental removed comments Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: stop pipelining VM PDs/PTs movesChristian König2018-09-192-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | We are going to need this for recoverable page fault handling and it makes shadow handling during GPU reset much more easier. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: remove fence fallbackChristian König2018-09-193-58/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DC doesn't seem to have a fallback path either. So when interrupts doesn't work any more we are pretty much busted no matter what. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: retrieve the updated clock table after ODEvan Quan2018-09-192-26/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | With OD settings applied, the clock table will be updated accordingly. We need to retrieve the new clock tables then. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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