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* | | drm/amd/powerplay: added I2C controller configurationEvan Quan2018-10-163-63/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPTABLE structure is stretched to add I2C controller configuration. Hold on the PPTABLE_V20_SMU_VERSION bump until the VBIOS is ready. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: update Vega20 SDMA golden settingEvan Quan2018-10-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Update SDMA golden settings. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Fix typo in amdgpu_vmid_mgr_initRex Zhu2018-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | fix a typo in for loop: i->j Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* | | drm/amd/display: fix bug of accessing invalid memorySu Sung Chung2018-10-151-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] A loop inside of build_evenly_distributed_points function that traverse through the array of points become an infinite loop when m_GammaUpdates does not get assigned to any value. [How] In DMColor, clear m_gammaIsValid bit just before writting all Zeromem for m_GammaUpdates, to prevent calling build_evenly_distributed_points before m_GammaUpdates gets assigned to some value. Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: correct SPDX identifier in amdgpu_trace_points.cJonathan Gray2018-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b24413180f5600bcb3bb70fbed5cf186b60864bd 'License cleanup: add SPDX GPL-2.0 license identifier to files with no license' incorrectly added "SPDX-License-Identifier: GPL-2.0" to a file with MIT license text. Change the SPDX identifier to match the license text. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Update SPG mode UVD status clearJames Zhu2018-10-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update Static Power Gate mode UVD status clear Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Set VCPU busy after gate power during vcn SPG startJames Zhu2018-10-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Set VCPU busy after gate power during vcn Static Power Gate start Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Apply new UMC enable for VNC DPG modeJames Zhu2018-10-121-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Apply new UMC enable for VNC Dynamic Power Gate mode Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Remove SPG mode unused steps during vcn startJames Zhu2018-10-121-28/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove Sitatic Power Gate mode unused steps during vcn start Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Add SPG mode Register XX checkJames Zhu2018-10-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Static Power Gate mode Register XX check Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Move SPG mode mc resume after MPC controlJames Zhu2018-10-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move Static Power Gate mode mc resume after MPC control Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Update SPG mode VCN global tilingJames Zhu2018-10-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update Static Power Gate mode VCN global tiling Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Update SPG mode VCN memory controlJames Zhu2018-10-121-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update Static Power Gate mode VCN memory control Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode startJames Zhu2018-10-121-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Apply new UMC enable for VNC Dynamic Power Gate mode start Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Remove DPG mode unused steps during vcn startJames Zhu2018-10-121-27/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove Dynamic Power Gate mode unused steps during VCN start Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Add DPG mode Register XX checkJames Zhu2018-10-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Dynamic Power Gate mode Register XX check Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Update DPG mode VCN global tiling registersJames Zhu2018-10-121-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update Dynamic Power Gate mode VCN global tiling registers Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Update DPG mode VCN memory controlJames Zhu2018-10-121-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update Dynamic Power Gate mode VCN memory control Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Reduce unnecessary local variableJames Zhu2018-10-121-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Reduce unnecessary local variable. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG mode stopJames Zhu2018-10-121-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ring write/read pointer check for VCN dynamic power gate mode stop,to make sure that no job is left in ring before turn off DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Update latest spg mode stop for VCNJames Zhu2018-10-121-15/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update latest static power gate mode stop function for VCN Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Update latest UVD_MPC register for VCNJames Zhu2018-10-121-12/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update latest UVD_MPC register for VCN. Use defined macro to replace value for readability. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn:Add new register offset/mask for VCNJames Zhu2018-10-122-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new register offset/mask for VCN to support latest VCN implementation. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/display: dm/amdgpu: make dp phy debugfs for eDPhersen wu2018-10-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] dp debugfs file does not exist for eDP under /sys/kernel/debug/dri/0/eDP-1. the root is phy debugfs is created for dp connector only. [HOW] for eDP connector, create phy debugfs too. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Set the default value about gds vmid0 sizeEmily Deng2018-10-121-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For sriov, when first run windows guest, then run linux guest, the gds vmid0 size will be reset to 0 by windows guest. So if the value has been reset to 0, then set the value to the default value in linux guest. v2: Fixed value instead of reading mmGDS_VMID0_SIZE. v3: Set the default value of the switch. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: hint when power profile setting is not supportedEvan Quan2018-10-121-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | Give user some hints when the power profile setting is not supported. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: translate power_profile mode to pplib workload typeEvan Quan2018-10-121-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | Correctly translate the power profile specified by user to workload type accepted by SMU fw. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: factor out some pptable helpersAlex Deucher2018-10-104-96/+70
| | | | | | | | | | | | | | | | | | | | | | | | Move copy_array helpers to smu_helper.c and share between vega12 and vega20. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: endian fixes for vega20_processpptables.cAlex Deucher2018-10-101-16/+25
| | | | | | | | | | | | | | | | | | | | | Properly swap data from vbios. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: endian fixes for vega12_processpptables.cAlex Deucher2018-10-101-12/+14
| | | | | | | | | | | | | | | | | | | | | Properly swap data from vbios. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: endian fixes for vega10_processpptables.cAlex Deucher2018-10-101-15/+15
| | | | | | | | | | | | | | | | | | | | | Properly swap data from vbios. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: remove set but not used variable 'header'YueHaibing2018-10-101-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c: In function 'amdgpu_ucode_init_bo': drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:431:39: warning: variable 'header' set but not used [-Wunused-but-set-variable] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: remove set but not used variable 'ring' in psp_v11_0_ring_stopYueHaibing2018-10-101-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/psp_v11_0.c: In function 'psp_v11_0_ring_stop': drivers/gpu/drm/amd/amdgpu/psp_v11_0.c:309:19: warning: variable 'ring' set but not used [-Wunused-but-set-variable] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdkfd: Remove set but not used variable 'preempt_all_queues'YueHaibing2018-10-101-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c: In function 'destroy_queue_cpsch': drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:1366:7: warning: variable 'preempt_all_queues' set but not used [-Wunused-but-set-variable] It never used since introduct in commit 992839ad64f2 ("drm/amdkfd: Add static user-mode queues support") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: fix missing break in switch statementsColin Ian King2018-10-105-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several switch statements that are missing break statements. Add missing breaks to handle any fall-throughs corner cases. Detected by CoverityScan, CID#1457175 ("Missing break in switch") Fixes: 18aafc59b106 ("drm/amd/powerplay: implement fw related smu interface for iceland.") Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Suppress keypresses from ACPI_VIDEO eventsLyude Paul2018-10-101-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we return NOTIFY_DONE for any event which we don't think is ours. However, many laptops will send more then just an ATIF event and will also send an ACPI_VIDEO_NOTIFY_PROBE event as well. Since we don't check for this, we return NOTIFY_DONE which causes a keypress for the ACPI event to be propogated to userspace. This is the equivalent of someone pressing the display key on a laptop every time there's a hotplug event. So, check for ACPI_VIDEO_NOTIFY_PROBE events and suppress keypresses from them. Signed-off-by: Lyude Paul <lyude@redhat.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Remove the direct fw loading support for sdma2.4Rex Zhu2018-10-101-42/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | sdma2.4 is only for iceland. For Vi, we don't maintain the direct fw loading. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Remove wrong fw loading type warningRex Zhu2018-10-101-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the warning message: "-1 is not supported on VI" the -1 is the default fw load type, mean auto. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2Rex Zhu2018-10-107-52/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the function of fw loading out of powerplay. Do fw loading between hw_init/resuem_phase1 and phase2 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: split ip hw_init into 2 phasesRex Zhu2018-10-101-13/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to do some IPs earlier to deal with ordering issues similar to how resume is split into two phases. Will do fw loading via smu/psp between the two phases. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Remove amdgpu_ucode_fini_boRex Zhu2018-10-104-26/+1
| | | | | | | | | | | | | | | | | | | | | | | | The variable clean is unnecessary. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functionsRex Zhu2018-10-103-29/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. one is for create/free bo when init/fini 2. one is for fill the bo before fw loading the ucode bo only need to be created when load driver and free when driver unload. when resume/reset, driver only need to re-fill the bo if the bo is allocated in vram. Suggested by Christian. v2: Return error when bo create failed. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Check late_init status before set cg/pg stateRex Zhu2018-10-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix cg/pg unexpected set in hw init failed case. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Refine function amdgpu_device_ip_late_initRex Zhu2018-10-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. only call late_init when hw_init successful, so check status.hw instand of status.valid in late_init. 2. set status.late_initialized true if late_init was not implemented. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Change AI gfx/sdma/smu init sequenceRex Zhu2018-10-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | initialize gfx/sdma before dpm features enabled. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Change SI/CI gfx/sdma/smu init sequenceRex Zhu2018-10-102-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | initialize gfx/sdma before dpm features enabled. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Limit the max mc address to hole startEmily Deng2018-10-101-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the vram_start is 0 case, the gart range will be from 0x0000FFFF00000000 to 0x0000FFFF1FFFFFFF, which will cause the engine hang. So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: fix CPDMA hang in PRT modeTao Zhou2018-10-101-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix CPDMA hang in PRT mode, set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in reg CP_DEBUG for GFX Affected ASICs: Vega10 Vega12 Raven Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Tested-by: Yukun.Li <yukun1.li@amd.com> Tested-by: Maciej.Jesionowski <maciej.jesionowski@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: add CP_DEBUG register definition for GC9.0Tao Zhou2018-10-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add CP_DEBUG register definition. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/display: RV2 DP MST 2nd display within daisy chain not light upHersen Wu2018-10-101-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RV2 resource is limit to 3 pipes. Limitation should apply to all HW blocks instead of front pipe. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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