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* drm/amdgpu/powerplay: add smu smc_table_manager callback for vega12Alex Deucher2018-09-263-12/+22
| | | | | | | For consistency with other asics. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: Move vega10_enable_smc_featuresAlex Deucher2018-09-266-12/+15
| | | | | | | to vega10_smumgr.c. For consistency with other vega parts. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add get_argument callback for vega20Alex Deucher2018-09-264-32/+15
| | | | | | | For consistency with other vega parts. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Return error immediately if load firmware failedRex Zhu2018-09-261-4/+6
| | | | | | | | this can avoid hard hang and be useful for debug. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Honour DC's clock limits on RvRex Zhu2018-09-261-8/+17
| | | | | | | | Honour display's request for min engine clock/memory clock. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: retrieve the updated clock table after ODEvan Quan2018-09-192-26/+90
| | | | | | | | | With OD settings applied, the clock table will be updated accordingly. We need to retrieve the new clock tables then. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update OD to take voltage value instead of offsetEvan Quan2018-09-194-35/+90
| | | | | | | | | | With the latest SMC fw, we are able to get the voltage value for specific frequency point. So, we update the OD relates to take absolute voltage instead of offset. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update OD feature judgementEvan Quan2018-09-192-26/+55
| | | | | | | | | Update the conditions to judge whether an OD feature should be supported on vega20. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: simplify Raven, Raven2, and Picasso handlingAlex Deucher2018-09-142-5/+4
| | | | | | | | | | Treat them all as Raven rather than adding a new picasso asic type. This simplifies a lot of code and also handles the case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu fw handling for picasso. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: disable raven2 force dpm level support (v2)Evan Quan2018-09-141-0/+6
| | | | | | | | | | It's not supported yet. v2: rebase (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: round up the Mhz convertion (v2)Evan Quan2018-09-141-2/+8
| | | | | | | | | | | Since the clock value there may be like 29999 10Khz. v2: rebase (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatibleEvan Quan2018-09-141-1/+2
| | | | | | | | | Check the raven2 version number as well. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add support of powerplay for picassoLikun Gao2018-09-142-4/+5
| | | | | | | | | add powerplay support for picasso, treat it the same as raven now. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: fix compile warning for wrong data type V2Evan Quan2018-09-101-2/+2
| | | | | | | | | | | do_div expects the 1st argument in 64bit instead of 32bit. Drop the usage of do_div as it seems unnecessary. V2: drop usage of do_div completely Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: correct data type to support under voltageEvan Quan2018-09-101-3/+3
| | | | | | | | | For under voltage, negative value will be applied to voltage offset. Update the data type to cover this case. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: added vega20 overdrive support V3Evan Quan2018-09-101-1/+288
| | | | | | | | | | | | | | | | | | Added vega20 overdrive support based on existing OD sysfs APIs. However, the OD logics are simplified on vega20. So, the behavior will be a little different and works only on some limited levels. V2: fix typo fix commit description revise error logs add support for clock OD V3: separate clock from voltage OD settings Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: OverDrive gfx domain voltage on TongaRex Zhu2018-08-271-0/+1
| | | | | | | | | | | | | | | Also ajust the gfx domain voltage on Tonga when user overdriver the voltage. For Tonga, Driver do not update user's setting to voltage table in smu, we only pick up a minimum value from voltage table that not less than the user's setting. v2: fix a typo Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: added voltage boot time calibrationEvan Quan2018-08-271-0/+10
| | | | | | | | | Run AFLL BTC after upload pptable and before enabling all smu features. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: remove max DCEFCLK limitationEvan Quan2018-08-271-3/+0
| | | | | | | | | The latest SMU fw removes the limitation that required UCLK >= DCEFCLK. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: allow slow switch only if NBPState enabledEvan Quan2018-08-271-1/+2
| | | | | | | | Otherwise there may be potential SMU performance issues. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: correct the argument for PPSMC_MSG_SetUclkFastSwitchEvan Quan2018-08-271-1/+1
| | | | | | | | | The argument was set wrongly. Fast/slow switch was asked when there is actually a slow/fast switch needed. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: avoid enabling/disabling uvd/vce dpm twiceEvan Quan2018-08-271-0/+6
| | | | | | | | | | For vega20, there are two UVD rings which share one powerplay instance. Under some case(two rings used parallel), the uvd dpm is disabled twice which causes the SMC hang. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: remove setting soc floor voltage before sending pptableEvan Quan2018-08-272-9/+1
| | | | | | | | | SOC voltage is not able to switch and forced to low 0.8V when running HEVC. Thus the test failed. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable fclk ss by defaultEvan Quan2018-08-271-1/+1
| | | | | | | | Set fclk ss as enabled on default. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update vega20 clocks threshold settings on power state adjustEvan Quan2018-08-271-0/+112
| | | | | | | | | UVD, VCE and SOC clocks need to be taken into consideration. Also, the thresholds need be updated correspondingly when stable power state is selected. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: revise vega20 PPSMC_MSG_SetSoftMin/[Max]ByFreq settingsEvan Quan2018-08-271-13/+96
| | | | | | | | | UVD, VCE and Socclk also need to be taken into consideration when setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: new interfaces for overdrive vega20 sclk and mclkEvan Quan2018-08-271-0/+169
| | | | | | | | Add support for the new SMU firmware interface for clock adjustment. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: initialize vega20 overdrive settingsEvan Quan2018-08-275-49/+403
| | | | | | | | | The initialized overdrive settings are taken from vbios and SMU( by PPSMC_MSG_TransferTableSmu2Dram). Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: conv the vega20 pstate sclk/mclk into necessary 10KHz unitEvan Quan2018-08-271-0/+3
| | | | | | | | Powerplay uses 10KHz units. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add vega20 pre_display_config_changed callbackEvan Quan2018-08-271-0/+41
| | | | | | | | | | | | | | fix possible handshake hang and video playback crash Corner cases: - Handshake between SMU and DCE causes hangs when CRTC is not enabled - System crash occurs when starting 4K playback with Movies and TV in an SLS configuration Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: export vega20 stable pstate clocksEvan Quan2018-08-271-1/+25
| | | | | | | | Needed for querying the stable pstate clocks. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: correct force clock level related settings for vega20 (v2)Evan Quan2018-08-271-45/+64
| | | | | | | | | | | | | | | | 1. The min/max level is determined by soft_min_level/soft_max_level. 2. Vega20 comes with pptable v3 which has no vdd related table(vdd_dep_on_socclk, vdd_dep_on_mclk) support. 3. Vega20 does not support separate fan feature control(enable or disable). v2: squash in fixes: - bug fix for force dpm level settings - fix wrong data type Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: init vega20 uvd/vce powergate status on dpm setupEvan Quan2018-08-271-0/+18
| | | | | | | | This is essentially necessary when uvd/vce dpm is not enabled yet. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: support workload profile query and setup for vega20Evan Quan2018-08-271-1/+192
| | | | | | | | Support the power profile API. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add the hw manager for vega20 (v3)Evan Quan2018-08-2710-2/+3956
| | | | | | | | | | | | | | | | | | | | | | | | hwmgr is the interface for the driver to setup state structures which are used by the smu for managing the power state. v2: squash in fixes: - update set_watermarks_for_clocks_ranges to use common code - drop unsupported apis - correct MAX_REGULAR_DPM_NUMBER value - multimonitor fixes - add check for vbios pptable version - revise dpm table setup - init fclk dpm state - Remove unused definition in vega20_hwmgr - support power limit setup - enable vega20 to honour DAL clock limits - comment out dump_table debugging v3: switch to SOC15 register access macros Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: new interfaces for ActivityMonitor table with SMUEvan Quan2018-08-272-0/+61
| | | | | | | | | Vega20 has a new activity monitor table that is stored in memory. Add API to get and set the new table. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add the smu manager for vega20 (v2)Evan Quan2018-08-273-1/+592
| | | | | | | | | | | | | | The SMU manager handles the driver interaction with the SMU which handles clock and voltage controls. v2: switch to SOC15 register access macros reserve space for ActivityMonitor table enable SMU fw loading Drop dead code from bringup Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add vega20_pptable.h (v2)Evan Quan2018-08-271-0/+140
| | | | | | | | v2: squash in table size fixes Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add vega20_ppsmc.h (v2)Evan Quan2018-08-271-0/+127
| | | | | | | | v2: update to latest. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add smu11_driver_if.h (v4)Evan Quan2018-08-271-0/+831
| | | | | | | | | | v2: cleanup v3: fit the latest 40.6 smc fw v4: update to latest. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add vega20_inc.h (v2)Evan Quan2018-08-271-0/+35
| | | | | | | | v2: use thm 11.0.2 headers Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay/vega10: enable AVFS control via ppfeaturemaskAlex Deucher2018-08-271-1/+2
| | | | | | | | Allow the user to disable AFVS via ppfeaturemask for debugging. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay/smu7: enable AVFS control via ppfeaturemaskAlex Deucher2018-08-271-1/+2
| | | | | | | | Allow the user to disable AFVS via ppfeaturemask for debugging. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: check vrefresh when when changing displaysAlex Deucher2018-08-278-1/+11
| | | | | | | | | | | | Compare the current vrefresh in addition to the number of displays when determining whether or not the smu needs updates when changing modes. The SMU needs to be updated if the vbi timeout changes due to a different refresh rate. Fixes flickering around mode changes in some cases on polaris parts. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/pp: endian fixes for processpptables.cAlex Deucher2018-08-271-14/+16
| | | | | | | | Properly swap when reading from the vbios. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/pp: endian fixes for process_pptables_v1_0.cAlex Deucher2018-08-271-97/+97
| | | | | | | | Properly swap when reading from the vbios. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Delete duplicated interface in hwmgr_funcRex Zhu2018-08-272-2/+0
| | | | | | | | | | gfx off support in smu can be via powergate_gfx interface. so remove the gfx_off_control interface. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Implement get_performance_level for legacy dgpuRex Zhu2018-08-273-1/+49
| | | | | | | | | | | | display can get clock info through this function. implement this function for vega10 and old asics. from vega12, there is no power state management, so need to add new interface to notify display the clock info Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Add ACP PG support in SMURex Zhu2018-08-273-1/+39
| | | | | | | | | when ACP block not enabled, we power off acp block to save power. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/powerplay: enable dpm under pass-throughYintian Tao2018-08-211-1/+3
| | | | | | | | | | | Repeat enable dpm under pass-through because there is no actually hardware-fini and real power-off when guest vm shutdown or reboot. Otherwise, under pass-through it will be failed to populate populate and upload SCLK MCLK DPM levels due to zero of pcie_speed_table.count. Signed-off-by: Yintian Tao <yttao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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