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* | drm/amd/display: Use MACROS instead of dm_loggerBhawanpreet Lakha2018-03-141-2/+1
| | | | | | | | | | | | | | | | Use DC_LOGGER macro for logs. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix check condition for edp power controlEric Yang2018-03-141-4/+10
| | | | | | | | | | | | | | | | | | | | | | Per discussion with VBIOS team, the orginal check is not correct in all cases on latest VBIOS. Additional check is needed. This change should maintain old behaviour on older VBIOS. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix takover from VGA modeBhawanpreet Lakha2018-03-141-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | HW Engineer's Notes: During switch from vga->extended, if we set the VGA_TEST_ENABLE and then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly. Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset VGA_TEST_ENABLE, to leave it in the same state as before. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Default HDMI6G support to true. Log VBIOS table error.Harry Wentland2018-03-051-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There have been many reports of Ellesmere and Baffin systems not being able to drive HDMI 4k60 due to the fact that we check the HDMI_6GB_EN bit from VBIOS table. Windows seems to not have this issue. On some systems we fail to the encoder cap info from VBIOS. In that case we should default to enabling HDMI6G support. This was tested by dwagner on https://bugs.freedesktop.org/show_bug.cgi?id=102820 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* | drm/amd/display: define DC_LOGGER for loggerBhawanpreet Lakha2018-03-057-56/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | Created a DC_LOGGER define. This is used to pass the logger into the macros. Anywhere we need to use the logger we need to define DC_LOGGER Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Use MACROS instead of dm_loggerBhawanpreet Lakha2018-03-057-31/+31
| | | | | | | | | | | | | | | | | | | | Created MACROS for all log levels. Also Replaced usage of dm_logger_write to the defined MACROS Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add regamma lut write mask to SOC baseLeo (Sunpeng) Li2018-03-051-0/+1
| | | | | | | | | | | | | | | | | | | | Mask and shift values for DCP0_REGAMMA_LUT_WRITE_EN_MASK were missing from XFM_COMMON_MASK_SH_LIST_SOC_BASE. Add it. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: provide an interface to query firmware versionAnthony Koo2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Rework DCE transform bit depth reduction programming.Leo (Sunpeng) Li2018-02-191-68/+36
| | | | | | | | | | | | | | | | | | | | Clear up the logic, and enable programming truncation as a bit reduction mode. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | amdgpu/dc: Fix enum mismatch in calls to program_color_matrix()Matthias Kaehlcke2018-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver passes GRAPHICS_CSC_ADJUST_TYPE_SW of type enum graphics_csc_adjust_type to program_color_matrix(), however the function expects a parameter of type enum grph_color_adjust_option. Supposedly the intention was to pass GRPH_COLOR_MATRIX_SW, which has the same value as GRAPHICS_CSC_ADJUST_TYPE_SW, so the mismatch didn't cause any trouble. Pass GRPH_COLOR_MATRIX_SW to program_color_matrix() instead of GRAPHICS_CSC_ADJUST_TYPE_SW, this also fixes the following warning when building the kernel with clang: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:1129:24: error: implicit conversion from enumeration type 'enum graphics_csc_adjust_type' to different enumeration type 'enum grph_color_adjust_option' [-Werror,-Wenum-conversion] xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: add eDP 1.2+ polling for T7Charlene Liu2018-02-191-1/+5
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: BL setting save/restoreCharlene Liu2018-02-191-0/+9
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: eDP sequence BL off first then DP blank.Charlene Liu2018-02-191-0/+3
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: disable az_clock_gating for endpoint register access onlyCharlene Liu2018-02-191-1/+17
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: clean up DCHUBBUB register definition in hwseqEric Bernstein2018-02-191-75/+1
| | | | | | | | | | | | | | | | | | | | Cleanup to remove unused register definition from hw sequencer header file since implementation moved from hw sequencer to dchubub file. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move opp reg access from hwss to opp module.Yongqiang Sun2018-02-191-6/+0
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: disablePSR in UpdatePlanes in PassiveLevelCharlene Liu2018-02-191-0/+3
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move dpp reg access from hwss to dpp module.Yongqiang Sun2018-02-191-8/+0
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix check for setting input TFAndrew Jiang2018-02-192-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | We no longer change the plane state pointer for full updates, and as such, we weren't setting the input transfer function and programming the degamma registers when we are supposed to. Check for a full update, an input TF change, or a gamma change in the update flags instead to correct this. Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Log which clocks are unsupportedHarry Wentland2018-02-191-1/+4
| | | | | | | | | | | | | | | | | | | | It would be useful to know which clocks are unsupported when logging an error message about unsupported clocks. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move hubp reg access from hwss to hubp module.Yongqiang Sun2018-02-191-12/+0
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Pass signal directly to enable_tmds_outputHarry Wentland2018-02-192-12/+6
| | | | | | | | | | | | | | | | | | | | This makes the check for HDMI and dual-link DVI a bit more straightforward. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move MAX_TMDS_CLOCK define to headerHarry Wentland2018-02-191-7/+0
| | | | | | | | | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Pass full 3x4 remap matrix for color transformKrunoslav Kovac2018-02-191-14/+3
| | | | | | | | | | | | | | Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Eliminate several Maximus-specific code pathsKen Chalmers2018-02-191-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows Maximus emulation to more closely mirror actual silicon execution. * Enable pool->base.display_clock creation on Maximus. * Enable rest of dce110_apply_ctx_to_hw on Maximus. * Remove apply_ctx_to_hw_fpga (no longer necessary with the full dce110_apply_ctx_to_hw enabled). * Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock for Maximus (this was the only fix-up necessary after enabling dce110_apply_ctx_to_hw; everything else works unmodified on Maximus). Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix Maximus pixel clock programmingKen Chalmers2018-02-191-11/+1
|/ | | | | | | | | Maximus testing now defaults to a 700 MHz emulated dispclk Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix check for whether dmcu fw is runningAnthony Koo2017-12-205-25/+42
| | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Move wait for hpd ready out from edp power control.Yongqiang Sun2017-12-141-15/+0
| | | | | | | | | | | | | | | | | | | | It may take over 200ms for wait hpd ready. To optimize the resume time, we can power on eDP in init_hw, wait for hpd ready when doing link training. also create separate eDP enable function to make sure eDP is powered up before doing and DPCD access, as HPD low will result in DPDC transaction failure. After optimization, setpowerstate 145ms -> 9.8ms, DPMS 387ms -> 18.9ms Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add dppclk to dcn_bw_clocksDmytro Laktyushkin2017-12-141-1/+2
| | | | | | | Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: try to find matching audio inst for enc inst firstCharlene Liu2017-12-141-3/+1
| | | | | | | | | | | | [Description] in eDP+ HDMI/DP clone or extended configuration, audio inst changed from inst 1 to inst0. No failure related this though, just playback device endpoint inst changed. Also remove one addition register read. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix seq issue: turn on clock before programming afmt.Charlene Liu2017-12-141-1/+3
| | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add license to MakefilesAlex Deucher2017-12-071-0/+21
| | | | | | | | | Was missing license text. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: DMCU and ABM maintenance and refactorAnthony Koo2017-12-062-27/+23
| | | | | | | | | Remove some globals that should really be per block state. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: A few more color indentation changesHarry Wentland2017-12-062-21/+17
| | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove unused register read in program_pwlHarry Wentland2017-12-061-3/+0
| | | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Bunch more color indentation cleanupsHarry Wentland2017-12-061-55/+49
| | | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove extra arr_points elementHarry Wentland2017-12-061-1/+1
| | | | | | | | | | | arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: remove unnecessary waits in dcn10Dmytro Laktyushkin2017-12-061-9/+0
| | | | | | | Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Bunch of indentation cleanups in color stuffHarry Wentland2017-12-061-106/+64
| | | | | | | | | | Trying to align with kernel coding style and make it a bit more readable. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Don't use dc_link in link_encoderAndrew Jiang2017-12-062-22/+17
| | | | | | | | | | | dc_link is at a higher level than link_encoder, and we only want higher-level components to be able to access lower-level ones, not the other way around. Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: correct DP is always in full range or bt609Charlene Liu2017-12-041-8/+17
| | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Move hdr_metadata from plane to streamAnthony Koo2017-12-041-1/+10
| | | | | | | | | | | | Need to move HDR Metadata from Surface to Stream since there is only one infoframe possible per stream. Also cleaning up some duplicate definitions. Signed-off-by: Anthony Koo <anthony.koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: DMCU FW loading from PSPAnthony Koo2017-12-042-7/+181
| | | | | | | | | | | | | | | | | | | | | | Update the programming sequence to allow DMCU firmware to be loaded by PSP. This code detects whether the firmware is loaded and does a check to verify the expected interface version and checks for correct response from micro controller. Added registry key method to allow force loading of firmware from kernel mode driver for test purposes. This is old method of firmware loading without PSP. Moved some init sequences into dc/dmcu. Changed loading sequence to initialize IRAM after firmware completely loaded. Firmware will now disable features that use IRAM until initialized. Signed-off-by: Anthony Koo <anthony.koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Bunch of smatch error and warning fixes in DCHarry Wentland2017-11-281-5/+5
| | | | | | | | | | | | | | | | | drivers/gpu/drm/amd/amdgpu/../display/dc/basics/log_helpers.c:79 dc_conn_log() error: buffer overflow 'signal_type_info_tbl' 10 <= 10 drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.c:266 bios_parser_get_dst_obj() error: uninitialized symbol 'id'. drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_audio.c:357 dce_aud_az_enable() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_resource.c:958 dcn10_acquire_idle_pipe_for_layer() error: we previously assumed 'head_pipe' could be null (see line 952) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: try to find matching audio inst for enc inst firstCharlene Liu2017-11-281-3/+1
| | | | | | | | | | | | [Description] in eDP+ HDMI/DP clone or extended configuration, audio inst changed from inst 1 to inst0. No failure related this though, just playback device endpoint inst changed. Also remove one addition register read. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix seq issue: turn on clock before programming afmt.Charlene Liu2017-11-281-0/+5
| | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix AZ clock not enabled before program AZ endpointCharlene Liu2017-11-131-2/+29
| | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* amdgpu/dc: fix indentation warning from smatch.Dave Airlie2017-11-072-21/+21
| | | | | | | | | | This fixes all the current smatch: warn: inconsistent indenting Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix warning about uninitialized variableHarry Wentland2017-10-211-1/+1
| | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add performance trace macro to dcDmytro Laktyushkin2017-10-211-5/+0
| | | | | | | Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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