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| | * | clk: qcom: common: Migrate to devm_* APIs for resets and clk providersStephen Boyd2017-11-011-24/+2
| | * | clk: Add devm_of_clk_add_hw_provider()/del_provider() APIsStephen Boyd2017-11-011-0/+52
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| * | Merge branch 'clk-const' into clk-nextStephen Boyd2017-11-1425-86/+86
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| | * | clk: make clk_init_data constBhumika Goyal2017-11-016-55/+55
| | * | clk: imx: make clk_ops constBhumika Goyal2017-11-014-5/+5
| | * | clk: mmp: make clk_ops constBhumika Goyal2017-11-013-3/+3
| | * | clk: hisilicon: make clk_ops constBhumika Goyal2017-11-013-4/+4
| | * | clk: mxs: make clk_ops constBhumika Goyal2017-11-012-2/+2
| | * | clk: sirf: make clk_ops constBhumika Goyal2017-11-011-6/+6
| | * | clk: spear: make clk_ops constBhumika Goyal2017-11-014-5/+5
| | * | CLK: SPEAr: make aux_clk_masks structures constBhumika Goyal2017-11-013-3/+3
| | * | CLK: SPEAr: make structure field and function argument as constBhumika Goyal2017-11-012-3/+3
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| * | Merge branch 'clk-sunxi' into clk-nextStephen Boyd2017-11-142-3/+1
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| | * | clk: sunxi: explicitly request exclusive reset controlPhilipp Zabel2017-11-011-1/+1
| | * | clk: sunxi: fix build warningCorentin LABBE2017-11-011-2/+0
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| * | Merge branch 'clk-hikey' into clk-nextStephen Boyd2017-11-144-6/+14
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| | * | clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'Shawn Guo2017-11-141-1/+11
| | * | clk: hisilicon: Delete an error message for a failed memory allocation in his...Markus Elfring2017-11-141-3/+1
| | * | clk: hi3660: fix incorrect uart3 clock freqencyZhong Kaihua2017-11-141-1/+1
| | * | clk: hi6220: mark clock cs_atb_syspll as criticalLeo Yan2017-11-011-1/+1
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| * | Merge tag 'tegra-for-4.15-clk-2' of git://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd2017-11-1413-66/+102
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| | * | clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen2017-11-011-2/+2
| | * | clk: tegra: dfll: Fix drvdata overwriting issueNicolin Chen2017-11-013-13/+11
| | * | clk: tegra: Fix cclk_lp divisor registerMichał Mirosław2017-11-011-1/+1
| | * | clk: tegra: Bump SCLK clock rate to 216 MHzDmitry Osipenko2017-11-011-1/+1
| | * | clk: tegra: Use common definition of APBDMA clock gateDmitry Osipenko2017-11-011-5/+1
| | * | clk: tegra: Correct parent of the APBDMA clockDmitry Osipenko2017-11-011-1/+1
| | * | clk: tegra: Add AHB DMA clock entryDmitry Osipenko2017-11-014-0/+4
| | * | clk: tegra: Mark APB clock as criticalJon Hunter2017-11-011-1/+1
| | * | clk: tegra: Make tegra_clk_pll_params __ro_after_initBhumika Goyal2017-10-191-8/+8
| | * | clk: tegra: Fix sor1_out clock implementationThierry Reding2017-10-192-16/+47
| | * | clk: tegra: Use tegra_clk_register_periph_data()Thierry Reding2017-10-194-13/+4
| | * | clk: tegra: Add peripheral clock registration helperThierry Reding2017-10-192-0/+11
| | * | clk: tegra: Check BPMP response return codeTimo Alho2017-10-191-5/+10
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| * | Merge tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd2017-10-313-9/+7
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| | * | clk: rockchip: use new cif/vdpu clock ids on rk3188Heiko Stuebner2017-10-141-6/+6
| | * | clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCsRomain Perier2017-10-141-1/+1
| | * | clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuc...Markus Elfring2017-09-281-2/+0
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| * | Merge tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd2017-10-3113-34/+214
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| | * | clk: renesas: rcar-gen3: Restore R clock during resumeGeert Uytterhoeven2017-10-201-2/+11
| | * | clk: renesas: rcar-gen3: Restore SDHI clocks during resumeGeert Uytterhoeven2017-10-201-13/+50
| | * | clk: renesas: div6: Restore clock state during resumeGeert Uytterhoeven2017-10-203-4/+40
| | * | clk: renesas: cpg-mssr: Add support to restore core clocks during resumeGeert Uytterhoeven2017-10-206-11/+23
| | * | clk: renesas: cpg-mssr: Restore module clocks during resumeGeert Uytterhoeven2017-10-201-0/+84
| | * | clk: renesas: cpg-mssr: Add du1 clock to R8A7745Fabrizio Castro2017-10-201-0/+1
| | * | clk: renesas: rz: clk-rz is meant for RZ/A1Geert Uytterhoeven2017-10-201-1/+1
| | * | clk: renesas: r8a77995: Correct parent clock of INTC-APGeert Uytterhoeven2017-10-161-1/+1
| | * | clk: renesas: r8a7796: Correct parent clock of INTC-APGeert Uytterhoeven2017-10-161-1/+1
| | * | clk: renesas: r8a7795: Correct parent clock of INTC-APGeert Uytterhoeven2017-10-161-1/+2
| * | | Merge tag 'meson-clk-for-4.15' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd2017-10-312-1/+297
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