| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: tegra: cclk_lp has a pllx/2 divider | Andrew Bresticker | 2014-02-17 | 1 | -1/+1 |
| | | | | | | | | | When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> | ||||
| * | clk: tegra: introduce common gen4 super clock | Peter De Schrijver | 2013-11-26 | 1 | -0/+149 |
| Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> | |||||
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| Talos™ II Linux sources for OpenBMC | Raptor Computing Systems |
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