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* Merge tag 'clk-for-linus-20151104' of ↵Linus Torvalds2015-11-053-63/+89
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The majority of the changes are driver updates and new device support. The core framework is mostly unchanged this time around, with only a couple patches to expose a clk provider API and make getting clk parent names from DT more robust. Driver updates: - Support for clock controllers found on Broadcom Northstar SoCs and bcm2835 SoC - Support for Allwinner audio clocks - A few cleanup patches for Tegra drivers and support for the highest DFLL frequencies on Tegra124 - Samsung exynos7 fixes and improvements - i.Mx SoC updates to add a few missing clocks and keep debug uart clocks on during kernel intialization - Some mediatek cleanups and support for more subsystem clocks - Support for msm8916 gpu/audio clocks and qcom's GDSC power domain controllers - A new driver for the Silabs si514 clock chip" * tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (143 commits) clk: qcom: msm8960: Fix dsi1/2 halt bits clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks clk: Add clk_hw_is_enabled() for use by clk providers clk: Add stubs for of_clk_*() APIs when CONFIG_OF=n clk: versatile-icst: fix memory leak clk: Remove clk_{register,unregister}_multiplier() clk: iproc: define Broadcom NS2 iProc clock binding clk: iproc: define Broadcom NSP iProc clock binding clk: ns2: add clock support for Broadcom Northstar 2 SoC clk: iproc: Separate status and control variables clk: iproc: Split off dig_filter clk: iproc: Add PLL base write function clk: nsp: add clock support for Broadcom Northstar Plus SoC clk: iproc: Add PWRCTRL support clk: cygnus: Convert all macros to all caps ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled clk: imx31: add missing of_node_put clk: imx27: add missing of_node_put clk: si5351: add missing of_node_put ...
| * clk: rockchip: save width in struct clk_fractional_dividerAndy Shevchenko2015-10-021-2/+4
| | | | | | | | | | | | | | | | | | The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when it will be switched to rational base approximation algorithm. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: rockchip: reset init state before mmc card initializationShawn Lin2015-10-011-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc host controller's IO input/output timing is unpredictable if bootloader execute tuning for HS200 mode. It might make kernel failed to initialize mmc card in identification mode. The root cause is tuning phase and degree setting for HS200 mode in bootloader aren't applicable to that of identification mode in kernel stage. Anyway, we can't force all bootloaders to reset tuning phase and degree setting before into kernel. Simply reset it in rockchip_clk_register_mmc. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: rockchip: don't use clk_ APIs in the pll init-callbackHeiko Stübner2015-10-011-61/+74
| | | | | | | | | | | | | | | | | | | | | | Separate the update of pll registers from the actual set_rate function so that the init callback does not need to access clk-API functions. As we now have separated the getting and setting of the pll parameters we can also directly use these new functions in other places too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * Merge branch 'clk-next' into v4.3-rc1Stephen Boyd2015-09-162-2/+13
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* | | clk: rockchip: Make calculations use roundingDouglas Anderson2015-10-261-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's use DIV_ROUND_CLOSEST for rounding, not just truncating division. This lets us get closer to the right rate. Before this: set_phase(86) delay_nums=26 reg[0xf000420c]=0x468 actual_degrees=83 set_phase(89) delay_nums=27 reg[0xf000420c]=0x46c actual_degrees=86 After this: set_phase(86) delay_nums=27 reg[0xf000420c]=0x46c actual_degrees=86 set_phase(89) delay_nums=28 reg[0xf000420c]=0x470 actual_degrees=90 Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | clk: rockchip: Allow more precision for some mmc clock phasesDouglas Anderson2015-10-261-15/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because of the inexact nature of the extra MMC delay elements (it's not possible to keep the phase monotonic and to also make phases (mod 90) > 70), we previously only allowed phases (mod 90) of 22.5, 45, and 67.5. But it's not the end of the world if the MMC clock phase goes non-monotonic. At most we'll be 25 degrees off. It's way better to test more phases to look for bad ones than to be 25 degrees off, because in the case of MMC really the point is to find bad phases and get as far asway from the as possible. If we get to test extra phases by going slightly non-monotonic then that might be fine. Worst case we would end up at a phases that's slight differnt than the one we wanted, but at least we'd still be quite far away from the a bad phase. Signed-off-by: Douglas Anderson <dianders@chromium.org> Fold in more precise variance-values of 44-77 instead of 40-80. Fold in the actual removal of the monotonic requirement and adapt patch message accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2015-09-191-0/+6
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A few driver fixes for tegra, rockchip, and st SoCs and a two-liner in the framework to avoid oops when get_parent ops return out of range values on tegra platforms" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x clk: check for invalid parent index of orphans in __clk_init() clk: tegra: dfll: Properly protect OPP list clk: rockchip: add critical clock for rk3368
| * | clk: rockchip: add critical clock for rk3368Heiko Stübner2015-09-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Again a result of the gpio-clock-liberation the rk3368 needs the pclk_pd_pmu marked as critical, to boot successfully. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2015-09-141-2/+7
|\ \ \ | |/ / | | / | |/ |/| | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A couple build fixes for drivers introduced in the merge window and a handful of patches to add more critical clocks on rockchip SoCs that are affected by newly introduced gpio clock handling" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188 clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks clk: rockchip: handle critical clocks after registering all clocks clk: Hi6220: separately build stub clock driver clk: h8s2678: Fix compile error
| * clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188Romain Perier2015-09-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Now that the rockchip clock subsystem does clock gating with GPIO banks, these are no longer enabled once during probe and no longer stay enabled for eternity. When all these clocks are disabled, the parent clock pclk_peri might be disabled too, as no other child claims it. So, we need to add pclk_peri to the critical clocks. Signed-off-by: Romain Perier <romain.perier@gmail.com> Tested-by: Michael Niewoehner <linux@mniewoehner.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: rockchip: add pclk_cpu to the list of rk3188 critical clocksMichael Niewoehner2015-09-101-0/+1
| | | | | | | | | | | | | | | | | | | | pclk_cpu needs to keep running because it is needed for devices like the act8865 regulator but with the recent gpio clock handling this is not always the case anymore. So add it to the list of critical clocks. Signed-off-by: Michael Niewoehner <linux@mniewoehner.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: rockchip: handle critical clocks after registering all clocksHeiko Stuebner2015-09-101-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the registration of critical clocks is done in the function shared between rk3066 and rk3188 clock trees. That results in them getting handled maybe before all of them are registered. Therefore move the critical clock handling down to the end of the soc- specific clock registration function, so that all clocks are registered before they're maybe handled as critical clock. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Michael Niewoehner <linux@mniewoehner.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge tag 'pinctrl-v4.3-1' of ↵Linus Torvalds2015-09-041-0/+1
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.3 development cycle. Like with GPIO it's a lot of stuff. If my subsystems are any sign of the overall tempo of the kernel v4.3 will be a gigantic diff. [ It looks like 4.3 is calmer than 4.2 in most other subsystems, but we'll see - Linus ] Core changes: - It is possible configure groups in debugfs. - Consolidation of chained IRQ handler install/remove replacing all call sites where irq_set_handler_data() and irq_set_chained_handler() were done in succession with a combined call to irq_set_chained_handler_and_data(). This series was created by Thomas Gleixner after the problem was observed by Russell King. - Tglx also made another series of patches switching __irq_set_handler_locked() for irq_set_handler_locked() which is way cleaner. - Tglx also wrote a good bunch of patches to make use of irq_desc_get_xxx() accessors and avoid looking up irq_descs from IRQ numbers. The goal is to get rid of the irq number from the handlers in the IRQ flow which is nice. Driver feature enhancements: - Power management support for the SiRF SoC Atlas 7. - Power down support for the Qualcomm driver. - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks in IRQ handlers to play nice with the realtime patch set. - Rework and new modes handling for Qualcomm SPMI-MPP. - Pinconf power source config for SH PFC. New drivers and subdrivers: - A new driver for Conexant Digicolor CX92755. - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support. - Reverse-egineered the S/PDIF settings for the Allwinner sun4i driver. - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs - A new Freescale i.mx6ul subdriver. Cleanup: - Remove platform data support in a number of SH PFC subdrivers" * tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits) pinctrl: at91: fix null pointer dereference pinctrl: mediatek: Implement wake handler and suspend resume pinctrl: mediatek: Fix multiple registration issue. pinctrl: sh-pfc: r8a7794: add USB pin groups pinctrl: at91: Use generic irq_{request,release}_resources() pinctrl: cherryview: Use raw_spinlock for locking pinctrl: baytrail: Use raw_spinlock for locking pinctrl: imx6ul: Remove .owner field pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks pinctrl: sun4i: add spdif to pin description. pinctrl: atlas7: clear ugly branch statements for pull and drivestrength pinctrl: baytrail: Serialize all register access pinctrl: baytrail: Drop FSF mailing address pinctrl: rockchip: only enable gpio clock when it setting pinctrl/mediatek: fix spelling mistake in dev_err error message pinctrl: cherryview: Serialize all register access pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting pinctrl: nomadik: reflect current input value ...
| * clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocksHeiko Stuebner2015-08-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | pclk_pd_pmu needs to keep running and with the upcoming gpio clock handling this is not always the case anymore. So add it to the list of critical clocks for now. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | clk: rockchip: register pll mux before pll itselfHeiko Stuebner2015-08-241-31/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The structure is xin24m -> pll -> pll-mux (xin24m,pll,xin32k). The pll does have an init callback to make sure the boot-selected frequency is using the expected pll settings and resets the same frequency using the values provided in the driver if necessary. The setting itself also involves remuxing the pll-mux temporarily to the xin24m source to let the new pll rate settle. Until now this worked flawlessly, even when it had the flaw of accessing the mux settings before the mux actually got registered. With the recent clock-core conversions this flaw became apparent in null pointer dereference in [<c03fc400>] (clk_hw_get_num_parents) from [<c0400df0>] (clk_mux_get_parent+0x14/0xc8) [<c0400ddc>] (clk_mux_get_parent) from [<c040246c>] (rockchip_rk3066_pll_set_rate+0xd8/0x320) So to fix that, simply register the pll-mux before the pll, so that it will be fully initialized when the pll clock executes its init- callback and possibly touches the pll-mux clock. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd2015-08-242-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script. @@ struct clk_hw *E; @@ -__clk_get_name(E->clk) +clk_hw_get_name(E) Acked-by: Heiko Stuebner <heiko@sntech.de> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Thierry Reding <treding@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Bresticker <abrestic@chromium.org> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Kevin Cernekee <cernekee@chromium.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: Convert to clk_hw based provider APIsStephen Boyd2015-08-241-9/+9
| | | | | | | | | | | | | | | | We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: Fix SPIF special clock definitionSjoerd Simons2015-08-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Neither spdif_src nor spdif_pll exists, judging by the vendor kernel in both cases spdif_pre was meant. This brings the naming in line and hierachy in line with that of sclk_i2s0. Also allow sclk_spdif and spdif_frac to change their parents rate as that the upstream dividers are purely there to feed sclk_spdif Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | clk: rockchip: Fix PLL bandwidthDouglas Anderson2015-07-284-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the TRM we see that BWADJ is "a 12-bit bus that selects the values 1-4096 for the bandwidth divider (NB)": NB = BWADJ[11:0] + 1 The recommended setting of NB: NB = NF / 2. So: NB = NF / 2 BWADJ[11:0] + 1 = NF / 2 BWADJ[11:0] = NF / 2 - 1 Right now, we have: { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ .bwadj = (_nf >> 1), \ } That means we set bwadj to NF / 2, not NF / 2 - 1 All of this is a bit confusing because we specify "NR" (the 1-based value), "NF" (the 1-based value), "NO" (the 1-based value), but "BWADJ" (the 0-based value) instead of "NB" (the 1-based value). Let's change to working with "NB" and fix the off by one error. This may affect PLL jitter in a small way (hopefully for the better). Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-285-3/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
| * | clk: rockchip: Properly include clk.hStephen Boyd2015-07-205-3/+5
| |/ | | | | | | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h if it's actually used. Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: add rk3368 clock controllerHeiko Stuebner2015-07-063-0/+898
| | | | | | | | | | | | | | Describe the clock tree and software resets of the rk3368 ARM64 SoC Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: define the inverters of rk3066/rk3188 and rk3288Heiko Stuebner2015-07-062-2/+14
| | | | | | | | | | | | | | | | Both soc series' have inverters on the hsadc and camera interface clock paths. So define them using the newly added inverter type. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: fix issues in the mmc-phase clockHeiko Stuebner2015-07-061-3/+3
| | | | | | | | | | | | | | | | | | The review for the new inverter clock type uncovered some issues (missing headers and name handling) that are also present in the mmc-phase clock type, I got (to much) inspiration from. Fix these there too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: add support for phase invertersHeiko Stuebner2015-07-064-0/+144
| | | | | | | | | | | | | | | | | | Most Rockchip socs have optional phase inverters connected to some clocks that move the clock-phase by 180 degrees. Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Dropped lazy part of commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variantHeiko Stuebner2015-07-061-0/+20
| | | | | | | | | | | | | | | | A clock branch consisting of a mux and divider with non-standard divider values. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: protect register macros against multipart valuesHeiko Stuebner2015-07-061-8/+8
| | | | | | | | | | | | | | | | | | | | The macros calculate the correct offset from the id in the parameter. If this parameter does not consist of a single number, the calculation will return wrong registers in the best case or create unaligned accesses in the worst case. So protect the calculations against such values. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: fix faulty vip parent name on rk3288Heiko Stuebner2015-07-061-2/+2
| | | | | | | | | | | | | | | | | | The video input processor (vip) was called camera interface (cif) on older socs which seems to have resulted in a copy'n'paste error when creating the rk3288 camera clocks. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_macHeiko Stuebner2015-07-061-1/+1
|/ | | | | | | | | | | | | | | | | The dwmac ethernet controller on the rk3288 supports phys connected via rgmii and rmii. With rgmii phys it is expected that the mac clock is provided externally while with rmii phys the clock can be external but also generated from the plls. In the later case it of course needs be at 50MHz, which gets set from the dwmac_rk driver. As most devices use a rgmii phy it never surfaced so far that the mac clk mux, doesn't go up one lever to the pll clock in the rmii case with internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag, and thus will not set the correct frequency in most cases. Fixes: b9e4ba541607 ("clk: rockchip: add clock controller for rk3288") Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: make several parent names constUwe Kleine-König2015-06-045-20/+20
| | | | | | | | | | | Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: rockchip: Staticize file-scope declarationsKrzysztof Kozlowski2015-05-052-2/+2
| | | | | | | Add missing static to local (file-scope only) symbols. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: don't use __initconst for non-const arraysUwe Kleine-König2015-04-124-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds2015-02-211-13/+35
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
| * Merge tag 'v3.20-rockchip-clk1' of ↵Michael Turquette2015-01-271-13/+35
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next The two big changes are the additional of the watchdog clock, which we currently only "fake" as the clock gate control is living in a very strange place, but the watchdog driver needs to read the clock rate from it and the setting of rk3288 plls to slow mode upon suspend. Other than that some more exported clocks and a CLK_SET_RATE_PARENT flag for the uart clocks.
| | * clk: rockchip: add a dummy clock for the watchdog pclk on rk3288Heiko Stuebner2015-01-221-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pclk supplying the watchdog is controlled via the SGRF register area. Currently we don't have any clock-type handling external clock bits like this one. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: add PVTM clocks on rk3288huang lin2015-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Process-Voltage-Temperatiure Monitor block on RK3288 has two clocks: PVTM_CORE and PVTM_GPU. Signed-off-by: Huang Lin <hl@rock-chips.com> Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: use the clock ID for usbphy480m_srcKever Yang2015-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use the clock ID for usbphy480m_src so that we can find this clock node in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow modeDoug Anderson2014-12-311-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've been seeing some crashes at resume time on rk3288-based systems. On some machines they simply never wake up from suspend. Symptoms include: - System clearly got to sleep OK. Power consumption is low, the PWM for the PWM regulator has stopped, and the "global_pwroff" output shows that the system is down. - When system tries to wake up power consumption goes up. - No kernel resume code (which was left in PMU SRAM) ran. We added some basic logging to this code (write to a location in SRAM right at resume time) and didn't see the logging run. It appears that we can fix the problem by slowing down APLL before we suspend. On the system I tested things seemed reliable if I disabled 1.8GHz and 1.7GHz. The Mask ROM itself tries to slow things down (which is why PLLs are in slow mode by the time we get to the kernel), but apparently it is crashing before it even gets there. We'll be super paranoid and not just go down to 1.6GHz but we'll match what the Mask ROM seems to be doing and go into slow mode. We'll also be safe and put all PLLs (not just APLL) into slow mode (well, except DPLL which is needed for SDRAM). We'll even put NPLL into slow mode which the Mask ROM didn't do (not that it's used for much important stuff at early resume time). Note that the old Rockchip reference code did something just like this, though they jammed it into pm.c instead of putting it in the syscore ops of the clock driver. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocksDoug Anderson2014-12-211-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | We'd like to be able to set the clock rate of the sclk_uart clocks and actually be able to achieve clock rates greater than 24MHz. To do this we need to be able to pass rate changes upward. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2015-01-273-25/+40
|\ \ \ | |/ / | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/boot/dts/imx6sx-sdb.dts net/sched/cls_bpf.c Two simple sets of overlapping changes. Signed-off-by: David S. Miller <davem@davemloft.net>
| * | clk: rockchip: fix deadlock possibility in cpuclkHeiko Stübner2015-01-171-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lockdep reported a possible deadlock between the cpuclk lock and for example the i2c driver. CPU0 CPU1 ---- ---- lock(clk_lock); local_irq_disable(); lock(&(&i2c->lock)->rlock); lock(clk_lock); <Interrupt> lock(&(&i2c->lock)->rlock); *** DEADLOCK *** The generic clock-types of the core ccf already use spin_lock_irqsave when touching clock registers, so do the same for the cpuclk. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: removed initialization of "flags"]
| * | clk: rockchip: fix rk3288 cpuclk core dividersHeiko Stuebner2014-12-281-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type for armclk) didn't take into account that the divider used on rk3288 are of the (n+1) type. The rk3066 and rk3188 socs use more complex divider types making it necessary for the list-elements to be the real register-values to write. Therefore reduce divider values in the table accordingly so that they really are the values that should be written to the registers and match the dividers actually specified for the rk3288. Reported-by: Sonny Rao <sonnyrao@chromium.org> Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Cc: stable@vger.kernel.org
| * | clk: rockchip: fix rk3066 pll lock bit locationHeiko Stuebner2014-12-281-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll. The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table. Fix this by defining separate pll definitions for rk3066 with the correct locking indices. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks") Tested-by: FUKAUMI Naoki <naobsd@gmail.com> Cc: stable@vger.kernel.org
| * | clk: rockchip: Fix clock gate for rk3188 hclk_emem_periRomain Perier2014-12-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not disable clock gate "hclk_emem_peri", otherwise EMAC clocks no longer work and it breaks ethernet on RK3066 and RK3188. It fixes a regression introduced by commit 78eaf6095cc7 ("clk: rockchip: disable unused clocks"). Signed-off-by: Romain Perier <romain.perier@gmail.com> Fixes: 78eaf6095cc7 ("clk: rockchip: disable unused clocks") Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB HostJulien CHAUVEAU2014-12-211-4/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds CLK_IGNORE_UNUSED flag to hclk_usb_peri, hclk_usbotg0 and hclk_usbotg1 because these clocks must remain enabled to use the USB controllers in host mode. This fixes a regression introduced by commit 78eaf6095cc7 ("clk: rockchip: disable unused clocks"). Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> Fixes: 78eaf6095cc7 ("clk: rockchip: disable unused clocks") Reviewed-by: Romain Perier <romain.perier@gmail.com> Tested-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | GMAC: modify CRU config for Rockchip RK3288 SoCs integrated GMACRoger Chen2014-12-311-7/+7
|/ | | | | | | | | | modify CRU config for GMAC driver changes since v2: 1. remove SCLK_MAC_PLL Signed-off-by: Roger Chen <roger.chen@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge tag 'v3.19-rockchip-clk2' of ↵Michael Turquette2014-11-287-50/+302
|\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next - clock phase setting capability for the rk3288 mmc clocks - pll init to allow syncing to actual rate table values - some more exported clocks - fixes for some clocks (typos etc) all of them not yet used in actual drivers
| * clk: rockchip: Add support for the mmc clock phases using the frameworkAlexandru M Stan2014-11-285-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the 2 physical clocks for the mmc (drive and sample). They're mostly there for the phase properties, but they also show the true clock (by dividing by RK3288_MMC_CLKGEN_DIV). The drive and sample phases are generated by dividing an upstream parent clock by 2, this allows us to adjust the phase by 90 deg. There's also an option to have up to 255 delay elements (40-80 picoseconds long). This driver uses those elements (under the assumption that they're 60 ps long) to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as 90 deg if the delay elements are as big as 80 ps, so a finer division (smaller than 22.5) was not picked because the phase might not be monotonic anymore. Suggested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * clk: rockchip: rk3288 export i2s0_clkout for use in DTSonny Rao2014-11-281-1/+1
| | | | | | | | | | | | | | | | | | This exposes the clock that comes out of the i2s block which generally goes to the audio codec. Signed-off-by: Sonny Rao <sonnyrao@chromium.org> [removed CLK_SET_RATE_PARENT from original patch] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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