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* powerpc/44x: Add support for the AMCC APM821xx SoCTirumala Marri2010-10-131-0/+1
| | | | | | | | This patch adds CPU, device tree, defconfig and bluestone board support for APM821xx SoC. Signed-off-by: Tirumala R Marri <tmarri@apm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* AMCC PPC 460SX redwood SoC platform initial frameworkMadhulika Madishetty2009-02-141-0/+1
| | | | | | | | | | | | | This patch contains initial framework for the AMCC Redwood board. Signed-off-by: Madhulika Madishetty <mmadishetty@amcc.com> Signed-off-by: Tirumala Marri <tmarri@amcc.com> Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Vidhyananth Venkatasamy <vvenkatasamy@amcc.com> Signed-off-by: Preetesh Parekh <pparekh@amcc.com> Acked-by: Loc Ho <lho@amcc.com> Acked-by: Feng Kan <fkan@amcc.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/virtex5: Fix Virtex5 machine check handlingGrant Likely2008-12-051-0/+1
| | | | | | | | | | | | | The 440x5 core in the Virtex5 uses the 440A type machine check (ie, they have MCSRR0/MCSRR1). They thus need to call the appropriate fixup function to hook the right variant of the exception. Without this, all machine checks become fatal due to loss of context when entering the exception handler. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/44x: Fix 460EX/460GT machine check handlingBenjamin Herrenschmidt2008-11-131-1/+6
| | | | | | | | | | | | Those cores use the 440A type machine check (ie, they have MCSRR0/MCSRR1). They thus need to call the appropriate fixup function to hook the right variant of the exception. Without this, all machine checks become fatal due to loss of context when entering the exception handler. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc: Remove use of CONFIG_PPC_MERGEKumar Gala2008-08-041-6/+0
| | | | | | | | | Now that arch/ppc is gone and CONFIG_PPC_MERGE is always set, remove the dead code associated with !CONFIG_PPC_MERGE from arch/powerpc and include/asm-powerpc. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* Revert "[POWERPC] 4xx: Fix 460GT support to not enable FPU"Josh Boyer2008-06-111-0/+1
| | | | | | | | | This reverts commit acb0142bf01c0ebe18f09e37814451ee6a873e27. AMCC has indicated that the PPC 460GT does have FPU support. This revert enables the FPU for those chips again. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Fix 460GT support to not enable FPUStefan Roese2008-04-241-1/+0
| | | | | | | The AMCC 460GT doesn't have an FPU so let's not enable support for it. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Add AMCC 460EX/460GT support to cputable.c & cpu_setup_44x.SStefan Roese2008-03-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's to arch/powerpc. Currently those PPC's are still based on a 440 core and *not* a 460 core. Here some basic features of those SoC's: 460EX: - Up to 1.2GHz, 32kB L1 I-cache and D-cache, 256kB L2-cache, FPU - 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane) - 2 * GBit Ethernet with TCP/IP acceleration - USB 2.0 Host/Device OTG and Host interface - SATA controller - Optional security feature 460GT (only changes to 460EX): - 4 * GBit Ethernet with TCP/IP acceleration - RapidIO - No SATA - No USB Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Fix 440grx setup function to call 440A fixupJosh Boyer2007-12-231-1/+5
| | | | | | | The mechanism to do the setup for 440A cores changed recently. This fixes the 440grx setup function to call __fixup_440A_mcheck. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] Reworking machine check handling and Fix 440/440ABenjamin Herrenschmidt2007-12-231-0/+9
| | | | | | | | | | | | | | | This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaroundValentine Barshak2007-10-031-1/+24
| | | | | | | | | | Add a workaround for PowerPC 440EPx/GRx incorrect write to DDR SDRAM errata. Data can be written to wrong address in SDRAM when write pipelining enabled on plb0. We disable it in the cpu_setup for these processors at early init. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Move 440EP(x) FPU setup from head_44x to cpu_setup_4xxValentine Barshak2007-10-031-0/+14
| | | | | | | | | | The PowerPC 440EP(x) FPU init is currently done in head_44x under ifdefs. Since we should support more then one board in the same kernel, we move FPU initialization code from head_44x to cpu_setup_44x and add cpu_setup callbacks for 440EP(x). Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Introduce cpu_setup functionality to 44x platformValentine Barshak2007-10-031-0/+19
This adds cpu_setup functionality for ppc44x platform. Low level cpu-spefic initialization routines should be placed in cpu_setup_44x.S and a callback should be added to cputable. The cpu_setup is invoked by identify_cpu() function at early init. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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