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* Merge branch 'ralf-3.7' of ↵Ralf Baechle2012-09-2844-116/+2874
|\ | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.Steven J. Hill2012-09-131-0/+16
| | | | | | | | | | | | | | The EXT and INS instructions can be used to decrease code size and thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: uasm: Add INS and EXT instructions.Steven J. Hill2012-09-132-5/+20
| | | | | | | | | | | | | | These are MIPS32R2 instructions for merging and extracting bit fields from one GPR into another. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Avoid pipeline stalls on some MIPS32R2 cores.Steven J. Hill2012-09-131-1/+13
| | | | | | | | | | | | | | | | | | | | The architecture specification says that an EHB instruction is needed to avoid a hazard when writing TLB entries. However, some cores do not have this hazard, and thus the EHB instruction causes a costly pipeline stall. Detect these cores and do not use the EHB instruction. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Make VPE count to be one-based.Steven J. Hill2012-09-131-0/+1
| | | | | | | | | | | | | | When dealing with multiple VPEs, the count needs to be one-based for correct initialization of the GIC. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Add new end of interrupt functionality for GIC.Steven J. Hill2012-09-131-1/+1
| | | | | | | | | | | | Each platform should define its own 'gic_finish_irq' function. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Add EIC support for GIC.Steven J. Hill2012-09-132-8/+95
| | | | | | | | | | | | Add support to use an external interrupt controller with the GIC. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Code clean-ups for the GIC.Steven J. Hill2012-09-132-34/+26
| | | | | | | | | | | | Fix whitespace, beautify the code and remove debug statements. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Make GIC code platform independent.Steven J. Hill2012-09-134-72/+81
| | | | | | | | | | | | | | | | The GIC interrupt code is used by multiple platforms and the current code was half Malta dependent code. These changes abstract away the platform specific differences. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Changes to configuration files for SEAD-3 platform.Steven J. Hill2012-09-133-2/+155
| | | | | | | | | | | | | | Change MIPS configuration files to add the SEAD-3. Also add new default configuration file for a SEAD-3 kernel. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Add core files for MIPS SEAD-3 development platform.Steven J. Hill2012-09-1329-0/+2445
| | | | | | | | | | | | | | | | | | | | | | More information about the SEAD-3 platform can be found at <http://www.mips.com/products/development-kits/mips-sead-3/> on MTI's site. Currently, the M14K family of cores is what the SEAD-3 is utilised with. Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Add support for the 1074K core.Steven J. Hill2012-09-134-0/+28
| | | | | | | | Signed-off-by: Steven J. Hill <sjhill@mips.com>
* | Merge branch 'rixi-3.7' of ↵Ralf Baechle2012-09-2811-29/+35
|\ \ | | | | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * | MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill2012-09-138-29/+26
| | | | | | | | | | | | | | | | | | | | | | | | Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
| * | MIPS: Add base architecture support for RI and XI.Steven J. Hill2012-09-134-1/+10
| |/ | | | | | | | | | | | | | | | | | | | | Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
* | Merge branch 'broadcom' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-09-279-10/+400
|\ \ | | | | | | | | | mips-for-linux-next
| * | MIPS: BCM63XX: Create platform_device for USBDKevin Cernekee2012-08-305-1/+98
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Reviewed-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4111/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: BCM63XX: Add register and IRQ definitions for USB 2.0 deviceKevin Cernekee2012-08-302-1/+221
| | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4084/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: BCM63XX: Fix USB IRQ definitions for 6328Kevin Cernekee2012-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | OHCI/EHCI are in the high (second) word. Not currently used by any driver. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4026/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: BCM63XX: Add register definitions for USBD dependenciesKevin Cernekee2012-08-302-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The USB 2.0 device depends on some functionality in other blocks, such as GPIO and USBH. Add those register definitions here. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4025/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: BCM63XX: Add new IUDMA definitions needed for USBDKevin Cernekee2012-08-302-2/+14
| | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4083/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: BCM63XX: Move DMA descriptor definition into common header fileKevin Cernekee2012-08-301-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "IUDMA" engine used by bcm63xx_enet is also used by other blocks, such as the USB 2.0 device. Move the definitions into a common file so that they do not need to be duplicated in each driver. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4082/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: BCM63XX: Expose the USBH/USBD clocks on BCM6328/BCM6368Kevin Cernekee2012-08-301-1/+20
| |/ | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4022/ Signed-off-by: John Crispin <blogic@openwrt.org>
* | Merge branch 'ath79' of git://dev.phrozen.org/mips-next into mips-for-linux-nextRalf Baechle2012-09-273-36/+65
|\ \
| * | MIPS: ath79: register USB host controller on the DB120 boardGabor Juhos2012-08-281-0/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4173/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: ath79: add USB platform setup code for AR934XGabor Juhos2012-08-282-0/+35
| | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4172/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: ath79: use a helper function for USB resource initializationGabor Juhos2012-08-281-36/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This improves code readability, and ensures that all resource fields will be initialized correctly. Additionally, it helps to reduce the size of the kernel image by using uninitialized resource variables. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4171/ Signed-off-by: John Crispin <blogic@openwrt.org>
* | | Merge branch 'lantiq' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-09-2713-220/+287
|\ \ \ | | | | | | | | | | | | mips-for-linux-next
| * | | MIPS: lantiq: make use of __gpio_to_irqJohn Crispin2012-09-131-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpio_chip struct allows us to set a .to_irq callback. Once this is set we can rely on the generic __gpio_to_irq() function to map gpio->irq allowing more than one gpio_chip to register an interrupt Signed-off-by: John Crispin <blogic@openwrt.org>
| * | | OF: pinctrl: MIPS: lantiq: adds support for FALCON SoCJohn Crispin2012-09-132-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
| * | | OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl supportJohn Crispin2012-09-134-184/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
| * | | MIPS: lantiq: adds support for gptu timersJohn Crispin2012-08-232-1/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lantiq socs have a General Purpose Timer Unit (GPTU). This driver allows us to initialize the timers. The voice firmware needs these timers as a reference. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4236/
| * | | MIPS: lantiq: enable pci clk conditional for xrx200 SoCJohn Crispin2012-08-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The xrx200 SoC family has the same PCI clock register layout as the AR9. Enable the same quirk as for AR9 Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4235/
| * | | MIPS: lantiq: falcon clocks were not enabled properlyJohn Crispin2012-08-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a result of a non populated ->bits field inside the clock struct, the clock domains were never powered on the Falcon. Until now we only used domains that were also used and powered by the bootloader. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4234/
| * | | MIPS: lantiq: adds support for nmi and ejtag bootrom vectorsJohn Crispin2012-08-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register nmi and ejtag bootrom vectors for FALC-ON SoC. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4238/
| * | | MIPS: lantiq: external irq sources are not loaded properlyJohn Crispin2012-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for the external interrupt unit was broken when the code was converted to devicetree support. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4231/
| * | | MIPS: lantiq: dont register irq_chip for the irq cascadeJohn Crispin2012-08-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We dont want to register the irq_chip for the MIPS IRQ cascade. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4230/
| * | | MIPS: lantiq: timer irq can be different to 7John Crispin2012-08-231-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq code to be able to handle this. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4229/
| * | | MIPS: lantiq: split up IRQ IM rangesJohn Crispin2012-08-233-28/+36
| | |/ | |/| | | | | | | | | | | | | | | | | | | Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate the SVIP we need to support IM ranges that are scattered inside the register range. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4237/
* | | Merge branch 'cn6xxx-mgmt' of ↵Ralf Baechle2012-09-273-31/+66
|\ \ \ | | | | | | | | | | | | git://git.linux-mips.org/pub/scm/daney/upstream-daney into mips-for-linux-next
| * | | MIPS: Octeon: Add octeon_io_clk_delay() function.David Daney2012-08-313-31/+66
| | |/ | |/| | | | | | | | | | | | | | | | Also cleanup and fix octeon_init_cvmcount() Signed-off-by: David Daney <ddaney@caviumnetworks.com> Acked-by: David S. Miller <davem@davemloft.net>
* | | Merge branch 'cn68xx-ciu2' of ↵Ralf Baechle2012-09-2758-1416/+43816
|\ \ \ | | | | | | | | | | | | git://git.linux-mips.org/pub/scm/daney/upstream-daney into mips-for-linux-next
| * | | MIPS: OCTEON: Register ciu/ciu2 as the default irq_domain.David Daney2012-08-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This makes it possible to call irq_create_mapping(NULL, ??) Signed-off-by: David Daney <david.daney@cavium.com>
| * | | MIPS: Octeon: Make interrupt controller work with threaded handlers.David Daney2012-08-311-143/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For CIUv1 controllers, we were relying on all calls to the irq_chip functions to be done from the CPU that received the irq, and that they would all be done from interrupt contest. These assumptions do not hold for threaded handlers. We make all the masking actually mask the irq source, and use real raw_spin_locks instead of manually twiddling the Status[IE] bit. Signed-off-by: David Daney <david.daney@cavium.com>
| * | | MIPS: OCTEON: Add support for cn68XX interrupt controller.David Daney2012-08-312-24/+547
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The cn68XX has a new interrupt controller named CIU2, add support for this, and use it if cn68XX detected at runtime. Signed-off-by: David Daney <david.daney@cavium.com>
| * | | MIPS: OCTEON: Add OCTEON_IRQ_* definitions for cn68XX chips.David Daney2012-08-311-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | There are 64 workqueue, 32 watchdog, and 4 mbox. Signed-off-by: David Daney <david.daney@cavium.com>
| * | | MIPS: OCTEON: Update register definitions.David Daney2012-08-3138-1160/+42982
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <david.daney@cavium.com>
| * | | MIPS: OCTEON: Add detection of cnf71xx parts.David Daney2012-08-311-0/+18
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Also add cvmx_get_octeon_family(). Both of these are needed by the upcoming register definition refresh patch. Signed-off-by: David Daney <david.daney@cavium.com>
| * | MIPS: pci-ar724x: avoid data bus error due to a missing PCIe moduleGabor Juhos2012-08-231-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the controller has no PCIe module attached, accessing of the device configuration space causes a data bus error. Avoid this by checking the status of the PCIe link in advance, and indicate an error if the link is down. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4293/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Malta: Delete duplicate PCI fixup.Ralf Baechle2012-08-171-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2ec8663f9c03a96f2c328c7c483603c31d62ad37 (lmo) rsp. 497e5ff03f58583ada469db8a1aa34eced9dd63e (kernel.org) [MIPS: Malta: Move PIIX4 PCI fixup to where it belongs.] attempted to move this PCI fixup but really only added it at it's new location without deleting the old instance. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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