summaryrefslogtreecommitdiffstats
path: root/arch/mips/ralink/mt7620.c
Commit message (Collapse)AuthorAgeFilesLines
* MIPS: ralink: Add a few missing clocksJohn Crispin2016-01-201-0/+3
| | | | | | | Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11995/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Fix vendor string for mt7620John Crispin2016-01-201-1/+1
| | | | | | | | | | Ralink was acquired by Mediatek. Represent this in the cpuinfo. It apparently confused people. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11994/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: fix USB frequency scalingJohn Crispin2016-01-201-1/+1
| | | | | | | | | | | Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully correct. The logic for the SoC check got inverted. We need to check if it is not a MT76x8. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11992/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: MT7688 pinmux fixesJohn Crispin2016-01-201-30/+50
| | | | | | | | | | A few fixes to the pinmux data, 2 new muxes and a minor whitespace cleanup. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11991/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Remove check for CONFIG_PCI on non-PCI SoCsJohn Crispin2015-11-111-3/+0
| | | | | | | | | | | The code currently panics if PCI is enabled but the SoC has no PCI bus. This check is superfluous as the driver only loads if enabled in the devicetree. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11444/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Fix usb issue during frequency scalingJohn Crispin2015-11-111-0/+20
| | | | | | | | | | | | | If the USB HCD is running and the cpu is scaled too low, then the USB stops working. Increase the idle speed of the core to fix this if the kernel is built with USB support. The "magic" values are taken from the Ralink SDK Kernel. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11441/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Unify SoC id handlingJohn Crispin2015-11-111-9/+6
| | | | | | | | | This makes detection a lot easier for audio, wifi, ... drivers. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11440/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: Add support for mt7688John Crispin2015-11-111-6/+29
| | | | | | | | | MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: add mt7628an supportJohn Crispin2014-11-241-45/+231
| | | | | | Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: add support for MT7620nJohn Crispin2014-11-241-7/+13
| | | | | | | | This is the small version of MT7620a. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8030/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: cleanup the soc specific pinmux dataJohn Crispin2014-11-241-109/+50
| | | | | | | | | | Before we had a pinctrl driver we used a custom OF api. This patch converts the soc specific pinmux data to a new set of structs. We also add some new pinmux setings. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: add verbose pmu infoJohn Crispin2014-11-241-0/+26
| | | | | | | | Print the PMU and LDO settings on boot. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/7999/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Panic messages should not end in \n.Ralf Baechle2013-10-291-1/+1
| | | | | | | Panic() is going to add a \n itself and it's annoying if a panic message rolls of the screen on a device with no scrollback. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: mt7620: Add spi clock definitionJohn Crispin2013-09-041-0/+1
| | | | | | | | | | | | | Register a clock device for the SPI block of the MT7620 SoC. The clock device will be used by the SPI host controller driver to determine the base clock of the controller. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: mt7620: Add wdt clock definitionJohn Crispin2013-09-041-0/+1
| | | | | | | | | | | | | | | | | | | The watchdog driver of the SoC uses the clk API to get the clock associated with the watchdog device. However the MT7620 specific setup code does not register a clock for the watchdog device yet which leads to the following error: rt2880_wdt: probe of 10000120.watchdog failed with error -2 Register a clock device for the watchdog in order to avoid the error and make the watchdog usable. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5756/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: mt7620: Improve clock frequency detectionGabor Juhos2013-09-041-25/+175
| | | | | | | | | | | | | | | | | | | | | The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: mt7620: Add verbose ram infoJohn Crispin2013-09-041-0/+3
| | | | | | | | | Make the code print which of SDRAM, DDR1 or DDR2 was detected. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/5671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ralink: add memory definition for MT7620John Crispin2013-05-081-0/+20
| | | | | | | Populate struct soc_info with the data that describes our RAM window. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5183/
* MIPS: ralink: adds support for MT7620 SoC familyJohn Crispin2013-05-081-0/+214
Add support code for mt7620 SOC. The code detects the SoC and registers the clk / pinmux settings. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5177/
OpenPOWER on IntegriCloud