summaryrefslogtreecommitdiffstats
path: root/arch/arm
Commit message (Collapse)AuthorAgeFilesLines
* ARM: OMAP2+: Fix unmet direct dependencies for SERIAL_OMAPTony Lindgren2013-05-032-2/+2
| | | | | | | | | | | | | | | | | Commit 8a6201b9 (ARM: OMAP2+: Fix unmet direct dependencies for zoom for 8250 serial) fixed unmet direct dependencies for 8250, but failed to do the same for omap serial. This can cause the following warning: warning: (ARCH_OMAP2PLUS_TYPICAL) selects SERIAL_OMAP which has unmet direct dependencies (TTY && HAS_IOMEM && GENERIC_HARDIRQS && ARCH_OMAP2PLUS). We should not select drivers, they should be selected by the user. Fix the issue by removing the select and adding them to omap2plus_defconfig instead. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: ux500: always select ABX500_COREArnd Bergmann2013-05-031-0/+2
| | | | | | | | | | | | | | | | We are probably selecting more drivers than we should in ux500, but cleaning up that logic for good can be left for another time. Most of these could be converted into silent options in the future, since they are always enabled on ux500 and never needed elsewhere. As a fixup for 3.10, let's at least select the dependencies for the other drivers we already select, to make it consistent. warning: (UX500_SOC_COMMON) selects AB8500_CORE which has unmet direct dependencies (HAS_IOMEM && GENERIC_HARDIRQS && ABX500_CORE && MFD_DB8500_PRCMU) Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: SIRF: select SMP_ON_UP only on SMP buildsArnd Bergmann2013-05-031-1/+1
| | | | | | | | | | | Like all other platforms, we can only select SMP_ON_UP if SMP is also enabled. warning: (SOC_IMX31 && SOC_IMX35 && ARCH_MARCO) selects SMP_ON_UP which has unmet direct dependencies (SMP && !XIP_KERNEL) Cc: Barry Song <baohua.song@csr.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: SPEAr: conditionalize l2x0 supportArnd Bergmann2013-05-031-0/+2
| | | | | | | | | | | If the cache controller implementation is disabled at build time, we must not call any functions related to it. arch/arm/mach-spear/built-in.o: In function `spear13xx_l2x0_init': arch/arm/mach-spear/spear13xx.c:47: undefined reference to `l2x0_init' Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.linux@gmail.com>
* ARM: imx: build CPU suspend code only when neededArnd Bergmann2013-05-031-1/+1
| | | | | | | | | | | | | The ARM CPU suspend function has its own configuration symbol, which we need to use for conditionalizing any code calling into it as well. arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume': /git/arm-soc/arch/arm/mach-imx/headsmp.S:57: undefined reference to `cpu_resume' Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: OMAP: build SMP code only for OMAP4/5Arnd Bergmann2013-05-031-4/+4
| | | | | | | | | | | | | | | | | | | | | The OMAP platform code assumes that SMP is only ever enabled when CONFIG_ARCH_OMAP4 or CONFIG_SOC_OMAP5 is enabled, which is not necessarirly true in a multiplatform configuration. arch/arm/mach-omap2/built-in.o: In function `omap4_smp_prepare_cpus': :(.init.text+0x413c): undefined reference to `omap_get_wakeupgen_base' :(.init.text+0x415c): undefined reference to `omap_secure_apis_support' arch/arm/mach-omap2/built-in.o: In function `omap4_boot_secondary': :(.cpuinit.text+0x28): undefined reference to `omap_get_wakeupgen_base' :(.cpuinit.text+0x3c): undefined reference to `omap_secure_apis_support' arch/arm/mach-omap2/built-in.o: In function `omap4_cpu_die': :(.ref.text+0x8): undefined reference to `omap_get_wakeupgen_base' :(.ref.text+0x10): undefined reference to `omap_secure_apis_support' :(.ref.text+0x4c): undefined reference to `omap4_hotplug_cpu' :(.ref.text+0x50): undefined reference to `omap_secure_apis_support' Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tony Lindgren <tony@atomide.com>
* ARM: tegra: Tegra114 needs CPU_FREQ_TABLEArnd Bergmann2013-05-031-0/+1
| | | | | | | | | | | | | | Like the other Tegra SoCs using the same cpufreq driver, we have to enable CPU_FREQ_TABLE for this one. drivers/built-in.o: In function `tegra_cpu_exit': drivers/cpufreq/tegra-cpufreq.c:237: undefined reference to `cpufreq_frequency_table_cpuinfo' Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Hiroshi Doyu <hdoyu@nvidia.com>
* ARM: default machine descriptor for multiplatformArnd Bergmann2013-04-293-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we now have default implementations for init_time and init_irq, the init_machine callback is the only one that is not yet optional, but since simple DT based platforms all have the same of_platform_populate function call in there, we can consolidate them as well, and then actually boot with a completely empty machine_desc. Unofortunately we cannot just default to an empty init_machine: We cannot call of_platform_populate before init_machine because that does not work in case of auxdata, and we cannot call it after init_machine either because the machine might need to run code after adding the devices. To take the final step, this adds support for booting without defining any machine_desc whatsoever. For the case that CONFIG_MULTIPLATFORM is enabled, it adds a global machine descriptor that never matches any machine but is used as a fallback if nothing else matches. We assume that without CONFIG_MULTIPLATFORM, we only want to boot on the systems that the kernel is built for, so we still retain the build-time warning for missing machine descriptors and the run-time warning when the platform does not match in that case. In the case that we run on a multiplatform kernel and the machine provides a fully populated device tree, we attempt to keep booting, hoping that no machine specific callbacks are necessary. Finally, this also removes the misguided "select ARCH_VEXPRESS" that was only added to avoid a build error for allnoconfig kernels. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Cc: "Russell King - ARM Linux" <linux@arm.linux.org.uk> Cc: Rob Herring <robherring2@gmail.com>
* ARM: dts: exynops4210: really add universal_c210 dtsOlof Johansson2013-04-291-0/+352
| | | | | | | | I fumbled when resolving a merge conflict on application of commit 765d012c2389 (ARM: dts: exynos4210: Add basic dts file for universal_c210 board), and left out the dts source file. Here it is. Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: dts: exynos4210: Add basic dts file for universal_c210 boardTomasz Figa2013-04-281-0/+1
| | | | | | | | | | | | | | | | | | This patch adds basic device tree sources for Universal C210 board. Currently support includes: - eMMC - serial - max8952 and max8998 voltage regulators. - gpio-keys More support will be added in further patches. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: dts: exynos4: Add node for PWM deviceTomasz Figa2013-04-281-0/+8
| | | | | | | | | | This patch adds device tree node for PWM block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: SAMSUNG: Do not register legacy timer interrupts on ExynosTomasz Figa2013-04-282-17/+2
| | | | | | | | | | | | This patch removes legacy PWM timer interrupt initialization from exynos{4,5}_init_irq() functions, since it conflicts with internal interrupt handling of the new PWM clocksource driver. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: smp_twd: convert to use CLKSRC_OF initRob Herring2013-03-119-34/+17
| | | | | | | | | | | | | | | | | | | | | | Now that we have OF based init with CLKSRC_OF, convert smp_twd init function to use it and covert all callers of twd_local_timer_of_register. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: John Stultz <johnstul@us.ibm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-omap@vger.kernel.org Cc: spear-devel@list.st.com Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) ↵Ivan Djelic2013-03-071-41/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimizations Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on assumptions about the implementation of memset and similar functions. The current ARM optimized memset code does not return the value of its first argument, as is usually expected from standard implementations. For instance in the following function: void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter) { memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter)); waiter->magic = waiter; INIT_LIST_HEAD(&waiter->list); } compiled as: 800554d0 <debug_mutex_lock_common>: 800554d0: e92d4008 push {r3, lr} 800554d4: e1a00001 mov r0, r1 800554d8: e3a02010 mov r2, #16 ; 0x10 800554dc: e3a01011 mov r1, #17 ; 0x11 800554e0: eb04426e bl 80165ea0 <memset> 800554e4: e1a03000 mov r3, r0 800554e8: e583000c str r0, [r3, #12] 800554ec: e5830000 str r0, [r3] 800554f0: e5830004 str r0, [r3, #4] 800554f4: e8bd8008 pop {r3, pc} GCC assumes memset returns the value of pointer 'waiter' in register r0; causing register/memory corruptions. This patch fixes the return value of the assembly version of memset. It adds a 'mov' instruction and merges an additional load+store into existing load/store instructions. For ease of review, here is a breakdown of the patch into 4 simple steps: Step 1 ====== Perform the following substitutions: ip -> r8, then r0 -> ip, and insert 'mov ip, r0' as the first statement of the function. At this point, we have a memset() implementation returning the proper result, but corrupting r8 on some paths (the ones that were using ip). Step 2 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 1: save r8: - str lr, [sp, #-4]! + stmfd sp!, {r8, lr} and restore r8 on both exit paths: - ldmeqfd sp!, {pc} @ Now <64 bytes to go. + ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. (...) tst r2, #16 stmneia ip!, {r1, r3, r8, lr} - ldr lr, [sp], #4 + ldmfd sp!, {r8, lr} Step 3 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 0: save r8: - stmfd sp!, {r4-r7, lr} + stmfd sp!, {r4-r8, lr} and restore r8 on both exit paths: bgt 3b - ldmeqfd sp!, {r4-r7, pc} + ldmeqfd sp!, {r4-r8, pc} (...) tst r2, #16 stmneia ip!, {r4-r7} - ldmfd sp!, {r4-r7, lr} + ldmfd sp!, {r4-r8, lr} Step 4 ====== Rewrite register list "r4-r7, r8" as "r4-r8". Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7667/1: perf: Fix section mismatch on armpmu_init()Stephen Boyd2013-03-061-1/+1
| | | | | | | | | | | | | | | | | WARNING: vmlinux.o(.text+0xfb80): Section mismatch in reference from the function armpmu_register() to the function .init.text:armpmu_init() The function armpmu_register() references the function __init armpmu_init(). This is often because armpmu_register lacks a __init annotation or the annotation of armpmu_init is wrong. Just drop the __init marking on armpmu_init() because armpmu_register() no longer has an __init marking. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7666/1: decompressor: add -mno-single-pic-base for building the ↵Jonathan Austin2013-03-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | decompressor Before jumping to (position independent) C-code from the decompressor's assembler world we set-up the C environment. This setup currently does not set r9, which for arm-none-uclinux-uclibceabi toolchains is by default expected to be the PIC offset base register (IE should point to the beginning of the GOT). Currently, therefore, in order to build working kernels that use the decompressor it is necessary to use an arm-linux-gnueabi toolchain, or similar. uClinux toolchains cause a prefetch abort to occur at the beginning of the decompress_kernel function. This patch allows uClinux toolchains to build bootable zImages by forcing the -mno-single-pic-base option, which ensures that the location of the GOT is re-derived each time it is required, and r9 becomes free for use as a general purpose register. This has a small (4% in instruction terms) advantage over the alternative of setting r9 to point to the GOT before calling into the C-world. Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7665/1: Wire up kcmp syscallCyrill Gorcunov2013-03-032-2/+2
| | | | | | | | | | Wire up kcmp syscall for ability to proceed checkpoint/restore procedure on ARM platform. Signed-off-by: Alexander Kartashov <alekskartashov@parallels.com> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7664/1: perf: remove erroneous semicolon from event initialisationChen Gang2013-03-031-1/+1
| | | | | | | | | | | | | | | | Commit 9dcbf466559f ("ARM: perf: simplify __hw_perf_event_init err handling") tidied up the error handling code for perf event initialisation on ARM, but a copy-and-paste error left a dangling semicolon at the end of an if statement. This patch removes the broken semicolon, restoring the old group validation semantics. Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Chen Gang <gang.chen@asianux.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7663/1: perf: fix ARMv7 EVTYPE_MASK to include NSH bitWill Deacon2013-03-031-1/+1
| | | | | | | | | | | | Masked out PMXEVTYPER.NSH means that we can't enable profiling at PL2, regardless of the settings in the HDCR. This patch fixes the broken mask. Cc: <stable@vger.kernel.org> Reported-by: Christoffer Dall <cdall@cs.columbia.edu> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7662/1: hw_breakpoint: reset debug logic on secondary CPUs in s2ram resumeDietmar Eggemann2013-03-031-1/+1
| | | | | | | | | | We must mask out the CPU_TASKS_FROZEN bit so that reset_ctrl_regs is also called on a secondary CPU during s2ram resume, where only the boot CPU will receive the PM_EXIT notification. Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7661/1: mm: perform explicit branch predictor maintenance when requiredWill Deacon2013-03-034-1/+6
| | | | | | | | | | | | | | | | | | The ARM ARM requires branch predictor maintenance if, for a given ASID, the instructions at a specific virtual address appear to change. From the kernel's point of view, that means: - Changing the kernel's view of memory (e.g. switching to the identity map) - ASID rollover (since ASIDs will be re-allocated to new tasks) This patch adds explicit branch predictor maintenance when either of the two conditions above are met. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7660/1: tlb: add branch predictor maintenance operationsWill Deacon2013-03-032-6/+40
| | | | | | | | | | | | | | | The ARM architecture requires explicit branch predictor maintenance when updating an instruction stream for a given virtual address. In reality, this isn't so much of a burden because the branch predictor is flushed during the cache maintenance required to make the new instructions visible to the I-side of the processor. However, there are still some cases where explicit flushing is required, so add a local_bp_flush_all operation to deal with this. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7659/1: mm: make mm->context.id an atomic64_t variableWill Deacon2013-03-034-14/+19
| | | | | | | | | | | | | | | | | | | | | | | mm->context.id is updated under asid_lock when a new ASID is allocated to an mm_struct. However, it is also read without the lock when a task is being scheduled and checking whether or not the current ASID generation is up-to-date. If two threads of the same process are being scheduled in parallel and the bottom bits of the generation in their mm->context.id match the current generation (that is, the mm_struct has not been used for ~2^24 rollovers) then the non-atomic, lockless access to mm->context.id may yield the incorrect ASID. This patch fixes this issue by making mm->context.id and atomic64_t, ensuring that the generation is always read consistently. For code that only requires access to the ASID bits (e.g. TLB flushing by mm), then the value is accessed directly, which GCC converts to an ldrb. Cc: <stable@vger.kernel.org> # 3.8 Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7658/1: mm: fix race updating mm->context.id on ASID rolloverWill Deacon2013-03-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | | If a thread triggers an ASID rollover, other threads of the same process must be made to wait until the mm->context.id for the shared mm_struct has been updated to new generation and associated book-keeping (e.g. TLB invalidation) has ben performed. However, there is a *tiny* window where both mm->context.id and the relevant active_asids entry are updated to the new generation, but the TLB flush has not been performed, which could allow another thread to return to userspace with a dirty TLB, potentially leading to data corruption. In reality this will never occur because one CPU would need to perform a context-switch in the time it takes another to do a couple of atomic test/set operations but we should plug the race anyway. This patch moves the active_asids update until after the potential TLB flush on context-switch. Cc: <stable@vger.kernel.org> # 3.8 Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7657/1: head: fix swapper and idmap population with LPAE and big-endianWill Deacon2013-03-031-4/+22
| | | | | | | | | | | | | | | The LPAE page table format uses 64-bit descriptors, so we need to take endianness into account when populating the swapper and idmap tables during early initialisation. This patch ensures that we store the two words making up each page table entry in the correct order when running big-endian. Cc: <stable@vger.kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7655/1: smp_twd: make twd_local_timer_of_register() no-op for nosmpShawn Guo2013-03-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting a SMP build kernel with nosmp on kernel cmdline, the following fat warning will be hit. ------------[ cut here ]------------ WARNING: at arch/arm/kernel/smp_twd.c:345 twd_local_timer_of_register+0x7c/0x90() twd_local_timer_of_register failed (-6) Modules linked in: Backtrace: [<80011f14>] (dump_backtrace+0x0/0x10c) from [<8044dd30>] (dump_stack+0x18/0x1c) r7:805e9f58 r6:805ba84c r5:80539331 r4:00000159 [<8044dd18>] (dump_stack+0x0/0x1c) from [<80020fbc>] (warn_slowpath_common+0x54/0x6c) [<80020f68>] (warn_slowpath_common+0x0/0x6c) from [<80021078>] (warn_slowpath_fmt+0x38/0x40) r9:412fc09a r8:8fffffff r7:ffffffff r6:00000001 r5:80633b8c r4:80b32da8 [<80021040>] (warn_slowpath_fmt+0x0/0x40) from [<805ba84] (twd_local_timer_of_register+0x7c/0x90) r3:fffffffa r2:8053934b [<805ba7d0>] (twd_local_timer_of_register+0x0/0x90) from [<805c0bec>] (imx6q_timer_init+0x18/0x4c) r5:80633800 r4:8053b701 [<805c0bd4>] (imx6q_timer_init+0x0/0x4c) from [<805ba4e8>] (time_init+0x28/0x38) r5:80633800 r4:805dc0f4 [<805ba4c0>] (time_init+0x0/0x38) from [<805b6854>] (start_kernel+0x1a0/0x310) [<805b66b4>] (start_kernel+0x0/0x310) from [<10008044>] (0x10008044) r8:1000406a r7:805f3f8c r6:805dc0c4 r5:805f0518 r4:10c5387d ---[ end trace 1b75b31a2719ed1c ]--- Check (!is_smp() || !setup_max_cpus) in twd_local_timer_of_register() to make it be a no-op for the conditions, thus avoid above warning. Reported-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.idBen Dooks2013-03-031-1/+1
| | | | | | | Fix missing use of the asid macro when getting the ASID from the mm->context.id field. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7642/1: netx: bump IRQ offset to 64Linus Walleij2013-03-032-33/+33
| | | | | | | | | | The Netx IRQs offset from zero, which is illegal, since Linux IRQ 0 is NO_IRQ. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2013-03-038-28/+35
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull late ARM updates from Russell King: "Here is the late set of ARM updates for this merge window; in here is: - The ARM parts of the broadcast timer support, core parts merged through tglx's tree. This was left over from the previous merge to allow the dependency on tglx's tree to be resolved. - A fix to the VFP code which shows up on Raspberry Pi's, as well as fixing the fallout from a previous commit in this area. - A number of smaller fixes scattered throughout the ARM tree" * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: ARM: Fix broken commit 0cc41e4a21d43 corrupting kernel messages ARM: fix scheduling while atomic warning in alignment handling code ARM: VFP: fix emulation of second VFP instruction ARM: 7656/1: uImage: Error out on build of multiplatform without LOADADDR ARM: 7640/1: memory: tegra_ahb_enable_smmu() depends on TEGRA_IOMMU_SMMU ARM: 7654/1: Preserve L_PTE_VALID in pte_modify() ARM: 7653/2: do not scale loops_per_jiffy when using a constant delay clock ARM: 7651/1: remove unused smp_timer_broadcast #define
| *-. Merge branches 'devel-stable', 'fixes' and 'mmci' into for-linusRussell King2013-03-0314-34/+64
| |\ \
| | * | ARM: Fix broken commit 0cc41e4a21d43 corrupting kernel messagesRussell King2013-03-011-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0cc41e4a21d43 (arch: remove direct definitions of KERN_<LEVEL> uses) is broken - not enough thought was put into changing: .asciz "string" to .asciz "string1" "string2" The problem is that each string gets _separately_ NUL terminated, so the result is a string containing: "string1\0string2\0" rather than: "string1string2\0" With our new printk levels, this ends up as - eg, KERN_DEBUG "string": 0x01 0x00 0x07 0x00 "string" 0x00 which produces lots of \x01 in the kernel log. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: fix scheduling while atomic warning in alignment handling codeRussell King2013-02-251-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Paolo Pisati reports that IPv6 triggers this warning: BUG: scheduling while atomic: swapper/0/0/0x40000100 Modules linked in: [<c001b1c4>] (unwind_backtrace+0x0/0xf0) from [<c0503c5c>] (__schedule_bug+0x48/0x5c) [<c0503c5c>] (__schedule_bug+0x48/0x5c) from [<c0508608>] (__schedule+0x700/0x740) [<c0508608>] (__schedule+0x700/0x740) from [<c007007c>] (__cond_resched+0x24/0x34) [<c007007c>] (__cond_resched+0x24/0x34) from [<c05086dc>] (_cond_resched+0x3c/0x44) [<c05086dc>] (_cond_resched+0x3c/0x44) from [<c0021f6c>] (do_alignment+0x178/0x78c) [<c0021f6c>] (do_alignment+0x178/0x78c) from [<c00083e0>] (do_DataAbort+0x34/0x98) [<c00083e0>] (do_DataAbort+0x34/0x98) from [<c0509a60>] (__dabt_svc+0x40/0x60) Exception stack(0xc0763d70 to 0xc0763db8) 3d60: e97e805e e97e806e 2c000000 11000000 3d80: ea86bb00 0000002c 00000011 e97e807e c076d2a8 e97e805e e97e806e 0000002c 3da0: 3d000000 c0763dbc c04b98fc c02a8490 00000113 ffffffff [<c0509a60>] (__dabt_svc+0x40/0x60) from [<c02a8490>] (__csum_ipv6_magic+0x8/0xc8) Fix this by using probe_kernel_address() stead of __get_user(). Cc: <stable@vger.kernel.org> Reported-by: Paolo Pisati <p.pisati@gmail.com> Tested-by: Paolo Pisati <p.pisati@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: VFP: fix emulation of second VFP instructionRussell King2013-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Martin Storsjö reports that the sequence: ee312ac1 vsub.f32 s4, s3, s2 ee702ac0 vsub.f32 s5, s1, s0 e59f0028 ldr r0, [pc, #40] ee111a90 vmov r1, s3 on Raspberry Pi (implementor 41 architecture 1 part 20 variant b rev 5) where s3 is a denormal and s2 is zero results in incorrect behaviour - the instruction "vsub.f32 s5, s1, s0" is not executed: VFP: bounce: trigger ee111a90 fpexc d0000780 VFP: emulate: INST=0xee312ac1 SCR=0x00000000 ... As we can see, the instruction triggering the exception is the "vmov" instruction, and we emulate the "vsub.f32 s4, s3, s2" but fail to properly take account of the FPEXC_FP2V flag in FPEXC. This is because the test for the second instruction register being valid is bogus, and will always skip emulation of the second instruction. Cc: <stable@vger.kernel.org> Reported-by: Martin Storsjö <martin@martin.st> Tested-by: Martin Storsjö <martin@martin.st> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7656/1: uImage: Error out on build of multiplatform without LOADADDROlof Johansson2013-02-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On multiplatform kernels, $MACHINE will be empty so there will be no default LOADADDR. Fail to build the uImage target unless one is provided by the developer at build time. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7654/1: Preserve L_PTE_VALID in pte_modify()Catalin Marinas2013-02-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following commit 26ffd0d4 (ARM: mm: introduce present, faulting entries for PAGE_NONE), if a page has been mapped as PROT_NONE, the L_PTE_VALID bit is cleared by the set_pte_ext() code. With LPAE the software and hardware pte share the same location and subsequent modifications of pte range (change_protection()) will leave the L_PTE_VALID bit cleared. This patch adds the L_PTE_VALID bit to the newprot mask in pte_modify(). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Subash Patel <subash.rp@samsung.com> Tested-by: Subash Patel <subash.rp@samsung.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> # 3.8.x Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 7653/2: do not scale loops_per_jiffy when using a constant delay clockNicolas Pitre2013-02-213-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When udelay() is implemented using an architected timer, it is wrong to scale loops_per_jiffy when changing the CPU clock frequency since the timer clock remains constant. The lpj should probably become an implementation detail relevant to the CPU loop based delay routine only and more confined to it. In the mean time this is the minimal fix needed to have expected delays with the timer based implementation when cpufreq is also in use. Reported-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 7651/1: remove unused smp_timer_broadcast #defineMark Rutland2013-02-131-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The assignment of clock_event_device::broadcast can be done by timer core as of 12ad100046: "clockevents: Add generic timer broadcast function", and the arm code moved over to this as of 3d06770eef: "arm: Add generic timer broadcast support", but left a dangling #define when !CONFIG_GENERIC_TIMER_BROADCAST. This patch removes the now unused #define. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | Merge branch 'for-rmk/broadcast' of ↵Russell King2013-02-0455-238/+231
| |\ \ \ | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into devel-stable
* | \ \ \ Merge tag 'late-mvebu-rebased' of ↵Linus Torvalds2013-02-2842-329/+1195
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC mvebu platform changes from Olof Johansson: "This series contains changes for the Marvell EBU platforms (mvebu, orion, kirkwood, dove) that were not part of the first set of pull requests because of dependencies on the MMC tree, and being submitted a little late. Notable changes are: - More devices get moved out of board files into device tree descriptions. The remaining devices listed in there have patches that will get sent for 3.10, after which we can remove a lot of the board files entirely. We are doing the pinctrl and mmc drivers here, ethernet and PCI still remain. - SMP support for mvebu is improved with support for the local interrupt controller. - The Guruplug board file gets replaced with a DT description. Unfortunately, the dependency on the MMC tree turned out to be a much larger problem than expected, when the MMC maintainer rebased the patches in his tree that all of the patches in this branch are based on, which caused merge conflicts between the new and old versions of those patches. To work around the merge conflicts, this branch rebases all patches on top of the respective MMC patches that did get merged into 3.9. The patches are all identical to the versions that were part of linux-next, but have a new commit date." * tag 'late-mvebu-rebased' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (90 commits) arm: mvebu: enable the SD card slot on Armada 370 Reference Design board ARM: kirkwood: topkick: init mvsdio via DT ARM: kirkwood: nsa310: convert to pinctrl ARM: Kirkwood: topkick: Enable i2c bus. ARM: kirkwood: topkick: convert to pinctrl ARM: dove: convert serial DT nodes to clocks property arm: mvebu: Add SPI flash on Armada 370 DB board arm: mvebu: Add SPI flash on Armada XP-DB board arm: mvebu: Add SPI flash on Armada XP-GP board arm: mvebu: Add support for SPI controller in Armada 370/XP clocksource: update and move armada-370-xp-timer documentation to timer directory arm: mvebu: update DT to support local timers ARM: Dove: convert usb host controller to DT arm: mvebu: Enable USB controllers on Armada 370/XP boards arm: mvebu: Add support for USB host controllers in Armada 370/XP arm: mvebu: add button for OpenBlocks AX3-4 ARM: Kirkwood: Convert NS2 to gpio-poweroff. ARM: Kirkwood: Convert NSA310 I2C to device tree ARM: Kirkwood: Convert NSA310 to use gpio-poweroff driver ARM: Kirkwood: Convert NSA310 to DT based regulators. ...
| * | | | | arm: mvebu: enable the SD card slot on Armada 370 Reference Design boardFlorian Fainelli2013-02-281-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 370 Reference Design board has one SD card slot, directly connected to the SDIO IP of the SoC, so we enable this IP. there are no GPIOs for card-detect and write-protect so we do not specify any. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | ARM: kirkwood: topkick: init mvsdio via DTJason Cooper2013-02-282-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Andrew Lunn <andrew@lunn.ch>
| * | | | | ARM: kirkwood: nsa310: convert to pinctrlJason Cooper2013-02-284-35/+99
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | ARM: Kirkwood: topkick: Enable i2c bus.Andrew Lunn2013-02-281-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DT node for I2C and pinctrl hog for the pins. There appears to be an i2c bus on topkick with a device on it: i2cdetect 0 WARNING! This program can confuse your I2C bus, cause data loss and worse! I will probe file /dev/i2c-0. I will probe address range 0x03-0x77. Continue? [Y/n] y 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- 64 -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | ARM: kirkwood: topkick: convert to pinctrlJason Cooper2013-02-282-42/+90
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | ARM: dove: convert serial DT nodes to clocks propertySebastian Hesselbarth2013-02-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_serial now has support for using clocks property and we have a DT clock provider. This patch replaces the hard coded clock-frequency property with a clocks phandle to tclk. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | arm: mvebu: Add SPI flash on Armada 370 DB boardGregory CLEMENT2013-02-281-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for the SPI flash MX25l25635E which is present on the Armada 370 DB board. This flash stores the bootloader and its environment. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | arm: mvebu: Add SPI flash on Armada XP-DB boardGregory CLEMENT2013-02-281-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for the SPI flash M25P64 which is present on the Armada XP DB board. This flash stores the bootloader and its environment. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | arm: mvebu: Add SPI flash on Armada XP-GP boardEzequiel Garcia2013-02-281-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an SPI master device node for Armada XP-GP board. This master node is an SPI flash controller 'n25q128a13'. Since there is no 'partitions' node declared, one full sized partition named as the device will be created. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Lior Amsalem <alior@marvell.com> Tested-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | arm: mvebu: Add support for SPI controller in Armada 370/XPEzequiel Garcia2013-02-281-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armada 370 and Armada XP SoC has an SPI controller. This patch adds support for this controller in Armada 370 and Armada XP SoC common device tree files. Note that the Armada XP SPI register length is 0x50 bytes, while Armada 370 SPI register length is 0x28 bytes, so we choose the smaller of the two. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Lior Amsalem <alior@marvell.com> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | | | arm: mvebu: update DT to support local timersGregory CLEMENT2013-02-281-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the time-armada-370-xp support local timers, updated the device tree to take it into account. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
OpenPOWER on IntegriCloud