summaryrefslogtreecommitdiffstats
path: root/arch/arm
Commit message (Collapse)AuthorAgeFilesLines
* Lower clock frequency of FPGA I2C bus to mitigate read / write errorsdev-4.13Raptor Engineering Development Team2018-05-191-0/+1
|
* Update MAX31785 setings on Talos systemsRaptor Engineering Development Team2018-05-191-6/+12
| | | | | Enable faster fan ramp up/down to avoid overshoot / fan speed oscillations Disable unnecessary temperature sensor watchdog
* Remove explicit chassis reset binding on Talos systemsRaptor Engineering Development Team2018-05-191-6/+0
| | | | This allows the reset button service to bind to the GPIO
* Remove DD1 VCS workaround GPIO hogRaptor Engineering Development Team2018-05-191-6/+0
|
* Move the system speaker from PWM7 to GPION7 for software-mode beep ↵Raptor Engineering Development Team2018-05-191-7/+5
| | | | development The ASpeed device doesn't really support variable PWM frequencies, at least not enough for proper beep support
* Port commit e3fac12aa8172222281420bf2eb1b25b756e82c8 to TalosRaptor Engineering Development Team2018-05-191-1/+4
| | | | ARM: dts: aspeed: talos: Add w83773g temp sensor
* Port commit 052add4e0fd8d827b85382f584e53582ce621951 to TalosRaptor Engineering Development Team2018-05-191-0/+6
| | | | ARM: dts: aspeed: talos: hog GPIOS7
* Add chassis reset request input to BMC DTS for TalosRaptor Engineering Development Team2018-05-191-0/+6
|
* Add BMC ready LED output to Talos BMC device treeRaptor Engineering Development Team2018-05-191-0/+4
|
* Put Talos system fans into PWM mode by defaultRaptor Engineering Development Team2018-05-191-6/+6
|
* Update Talos device tree to match production hardwareRaptor Engineering Development Team2018-05-191-28/+5
|
* Put fans in RPM mode at startup on Talos systemsRaptor Engineering Development Team2018-05-191-0/+6
|
* Enable PWM7 for use with on-board piezo speakerRaptor Engineering Development Team2018-05-191-1/+1
|
* Enable MAX31785 fan controllerRaptor Engineering Development Team2018-05-191-2/+87
|
* Add Raptor Computing Systems Talos BMC setup and device tree filesRaptor Engineering Development Team2018-05-192-0/+302
|
* ARM: dts: aspeed: Use 24MHz fixed clock for pwmLei YU2018-05-182-2/+2
| | | | | | | | | | The aspeed pwm driver always sets the clock source to 24MHz, specify the fixed clock in device tree to make sure the driver is using the correct clock frequency to calculate the fan speed. OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* fsi/fsi-master-gpio: Add "no-gpio-delays" optionBenjamin Herrenschmidt2018-05-113-0/+3
| | | | | | | | | | | | | | | | | This adds support for an optional device-tree property that makes the driver skip all the delays around clocking the GPIOs and set it in the device-tree of common POWER9 based OpenPower platforms. This useful on chips like the AST2500 where the GPIO block is running at a fairly low clock frequency (25Mhz typically). In this case, the delays are unnecessary and due to the low precision of the timers, actually quite harmful in terms of performance. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Clean up sio registersJoel Stanley2018-05-111-19/+18
| | | | | | | | Remove the unnecessary reg property. Drop the 'rx' in the name, as this refers to a quirk in the datasheet and is not useful. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: configs: aspeed: Add watchdog sysfsEddie James2018-05-072-0/+2
| | | | | | | | | | | This kernel config adds sysfs entries for watchdog devices. This is needed in order to access the bootstatus sysfs file that will indicate whether or not the BMC has tripped the watchdog and subsequently switched sides. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Move random number deviceJoel Stanley2018-05-072-12/+12
| | | | | | | | | | Move the node out from under the syscon/simple-mfd. Being a child of this node causes the driver to fail to probe, as platform_get_resource returns NULL due to dev->num_resources being zero. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: romulus: Enable the GFX IPJoel Stanley2018-05-011-0/+12
| | | | | | | | | | | The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and enables the GFX node. OpenBMC-Staging-Count: 1 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add Inventec Lanyang BMCBrian Yang2018-04-262-0/+332
| | | | | | | | | The Inventec Lanyang is Power 9 platform with ast2500 BMC. Tested-by: Brian Yang <yang.brianc.w@inventec.com> Signed-off-by: Brian Yang <yang.brianc.w@inventec.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add Portwell Neptune machineAmithash Prasad2018-04-262-1/+161
| | | | | | | | | | | | Initial introduction of Portwell Neptune family equipped with Aspeed 2500 BMC SoC. Neptune is a x86 server development kit with a ASPEED ast2500 BMC manufactured by Portwell. Specifically, This adds the neptune platform device tree file including the flash layout used by the neptune machines. Signed-off-by: Amithash Prasad <amithash@fb.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Add DAC MUX userspace controlJoel Stanley2018-04-201-2/+6
| | | | | | | | | | | | | | | | | This exposes SCU2C "Misc. Control Register" bits 16 and 17 which control the input to the VGA DAC. They are used to select which graphics device drives the analog output: 00: VGA mode (default) 01: Graphics CRT mode 10: Pass-through mode from Video input port-A 11: Pass-through mode from Video input port-B We don't need the reg property, so remove it and the unit name. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: witherspoon: Enable the GFX IPJoel Stanley2018-04-201-0/+8
| | | | | | | | | | | | The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: ast2500-evb: Enable the GFX IPJoel Stanley2018-04-201-1/+20
| | | | | | | | | | | | The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Add resets and clocks to GFX nodeJoel Stanley2018-04-201-0/+4
| | | | | | | | | | The ast2500 has a reset for the CRT device that must be deasserted before it can be used. Similarly it has a clock gate for a clock called D1CLK that must be set to running. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* dts: aspeed-g5: Expose SuperIO scratch registersAndrew Jeffery2018-04-191-0/+88
| | | | | | OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
* dts: aspeed-g5: Expose VGA scratch registersAndrew Jeffery2018-04-191-0/+48
| | | | | | OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
* Merge tag 'drm-for-v4.14' into dev-4.13Joel Stanley2018-04-196-114/+63
|\ | | | | | | | | | | | | | | | | | | This is the DRM tree that was merged into the mainline 4.14 kernel. The ASPEED GFX DRM driver requires functionaliy that was included in this tree, so we merge it back into the 4.13 OpenBMC tree. This should have no impact on other parts of the BMC. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: OMAP2+: fix missing variable declarationArnd Bergmann2017-08-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function that was added doesn't actually build: arch/arm/mach-omap2/display.c: In function 'omapdss_init_fbdev': arch/arm/mach-omap2/display.c:184:2: error: 'r' undeclared (first use in this function) This adds a declaration for 'r' to fix it. Fixes: 5ce783025c82 ("ARM: OMAP2+: Don't register omapdss device for omapdrm") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * ARM: OMAP2+: Don't register omapdss device for omapdrmLaurent Pinchart2017-08-161-51/+60
| | | | | | | | | | | | | | | | | | | | | | The omapdrm driver doesn't need the omapdss device anymore. Although it can't be removed completely as the fbdev driver still requires it, we can condition its registration to the usage of the omapfb driver. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * ARM: OMAP2+: Remove unused omapdrm platform deviceLaurent Pinchart2017-08-164-62/+1
| | | | | | | | | | | | | | | | | | | | The omapdrm platform device is unused, as a replacement is now registered in the omapdss driver. Remove it. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * ARM: OMAP2+: Register SoC device attributes from machine .init()Laurent Pinchart2017-08-152-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SoC device attributes are registered with a call to soc_device_register() from the machine .init_late() operation, which is called from the late initcall, after all drivers built-in drivers have been probed. This results in the impossibility for drivers to use SoC device matching in their probe function. The omap_soc_device_init() function is safe to call from the machine .init() operation, as all data it depends on is initialized from the .init_early() operation. Move SoC device attribute registration to machine .init() like on all other ARM platforms. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* | ARM: dts: aspeed: romulus: Add id-button gpio keyLei YU2018-04-171-0/+6
| | | | | | | | | | | | OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: npcm: enable L2 cache in NPCM7xx architectureTomer Maimon2018-04-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure. At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments regarding the flags use in L2 cache module. - https://www.spinics.net/lists/arm-kernel/msg613212.html After checking again the L2 cache use in the NPCM7xx, the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE and it is done in the device tree: https://patchwork.kernel.org/patch/10063497/ L2 cache flag mask allowed all the flag option. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit d893c4de012ad586400d9ccf5143884eafd8d841) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: npcm: modify configuration for the NPCM7xx BMC.Tomer Maimon2018-04-112-30/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify configuration and MakeFile for the Nuvoton NPCM and NPCM7xx BMC. [arnd: took this one late, since it fixes some build problems with the original commit] Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit cd903711fd9dce808b5cc07e509135886d962b0c) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: dts: modify Nuvoton NPCM7xx device tree structureTomer Maimon2018-04-113-178/+190
| | | | | | | | | | | | | | | | | | | | | | Modify Nuvoton NPCM7xx device tree structure by adding nuvoton common nNPCM7xx device tree structure that include all common modules. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 518d2f43c358da2072948f64df99b1bd417288dc) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: dts: modify Makefile NPCM750 configuration nameTomer Maimon2018-04-111-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 82e9f1d1f87d23ae943f8508a720f482bc2de256) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: dts: modify clock binding in NPCM750 device treeTomer Maimon2018-04-111-14/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | Modify clock binding in a common device tree for all Nuvoton NPCM750 BMCs. Modify NPCM750 modules clock numbers accourding the new clock driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 016c366f505f96dce2a4d0e1e9075fe6e0dfad3e) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: dts: modify timer register size in NPCM750 device treeTomer Maimon2018-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | Modify timer register size in a common device tree for all Nuvoton NPCM750 BMCs. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 4828b20a0b89efba524eb34b3234d98683dbe108) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: dts: modify UART compatible name in NPCM750 device treeTomer Maimon2018-04-111-4/+4
| | | | | | | | | | | | | | | | | | | | Modify UART compatible name in a common device tree for all Nuvoton NPCM750 BMCs. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 33a5365900e9cf914cd1d2bdde1457b79b3e9ed9) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: dts: add watchdog device to NPCM750 device treeTomer Maimon2018-04-112-0/+28
| | | | | | | | | | | | | | | | | | | | | | Add watchdog device node to a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 1c4937eec91426014247b9ae8cb3f04935cd4865) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: dts: add Nuvoton NPCM750 device treeBrendan Higgins2018-04-113-0/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit d6bdd009c21db3f677dd1d1bbb8c20bc819074bc) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: npcm: add basic support for Nuvoton BMCsBrendan Higgins2018-04-117-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds basic support for the Nuvoton NPCM750 BMC. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 7bffa14c9aed5f788d3126271f0fd8758fbd129e) Signed-off-by: Joel Stanley <joel@jms.id.au>
* | ARM: dts: aspeed: Describe random number deviceJoel Stanley2018-03-282-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a random number generator that updates a register in the SCU every second. This is compatible with the timeriomem rng driver in the kernel. From the timeriomem_rng bindings: quality: estimated number of bits of true entropy per 1024 bits read from the rng. Defaults to zero which causes the kernel's default quality to be used instead. Note that the default quality is usually zero which disables using this rng to automatically fill the kernel's entropy pool. As to the recommended value for us to use: Rick Altherr <raltherr@google.com> wrote: > Quality is #bit of entropy per 1000 bits read. 100 is a > conservative value that was suggested by those in the know. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
* | ARM: dts: aspeed: witherspoon: set alternate bootEddie James2018-03-131-0/+4
| | | | | | | | | | | | | | | | | | Set watchdog 2 to boot from the alternate flash chip when the watchdog timer expires and the system is reset. This enables "brick protection." OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* | Revert "ARM: dts: power9-cfam: Update OCC hwmon compatible"Eddie James2018-03-071-2/+3
| | | | | | | | | | | | | | | | | | This reverts commit f370fa626a127aec50801dafcd595a2b5a47e482. The dts properties were correct for the OCC driver. OpenBMC-Staging-Count: 1 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* | ARM: dts: aspeed: Add Qualcomm Centriq 2400 REP BMCKen Chen2018-02-222-0/+226
| | | | | | | | | | | | | | | | | | The Qualcomm Centriq 2400 REP (Reference Evaluation Platform) is an aarch64 Armv8 server platform with an ast2520 BMC. Signed-off-by: Ken Chen <chen.kenyy@inventec.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* | ARM: dts: aspeed-palmetto: Enable rear UARTJoel Stanley2018-02-221-0/+15
| | | | | | | | | | | | | | | | | | The Palmetto BMC has a UART connected to a RS-232 transceiver designed to be used as a serial console for the host processor. It appears as a D-sub connector on the back of the chassis. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
OpenPOWER on IntegriCloud