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* ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after ↵Kevin Hilman2012-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hwmod reset Without runtime PM enabled, hwmod needs to leave all IP blocks in an enabled state by default so any driver access to the HW will succeed. This is accomplished by seting the postsetup_state to enabled for all hwmods during init when runtime PM is disabled. Currently, we have a special case for WDT in that its postsetup_state is always set to disabled. This is done so that the WDT is disabled and the timer is disarmed at boot in case there is no WDT driver. This also means that when runtime PM is disabled, if a WDT driver *is* built in the kernel, the kernel will crash on the first access to the WDT hardware. We can't simply leave the WDT module enabled, because the timer is armed by default after reset. That means that if there is no WDT driver initialzed or loaded before the timer expires, the kernel will reboot. To fix this, a custom reset method is added to the watchdog class of omap_hwmod. This method will *always* disarm the timer after hwmod reset. The WDT timer then will only be rearmed when/if the driver is loaded for the WDT. With the timer disarmed by default, we no longer need a special-case for the postsetup_state of WDT during init, so it is removed. Any platforms wishing to ensure the watchdog remains armed across the entire boot boot can simply disable the reset-on-init feature of the watchdog hwmod using omap_hwmod_no_setup_reset(). Tested on 3530/Overo, 4430/Panda. NOTE: on 4430, the hwmod OCP reset does not seem to rearm the timer as documented in the TRM (and what happens on OMAP3.) I noticed this because testing the HWMOD_INIT_NO_RESET feature with no driver loaded, I expected a reboot part way through the boot, but did not see a reboot. Adding some debug to read the counter, I verified that right after OCP softreset, the counter is not firing. After writing the magic start sequence, the timer starts counting. This means that the timer disarm sequence added here does not seem to be needed for 4430, but is technically the correct way to ensure the timer is disarmed, so it is left in for OMAP4. Special thanks to Paul Walmsley for helping brainstorm ideas to fix this problem. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [paul@pwsan.com: updated the omap2_wd_timer_reset() function in the wake of commit 3c55c1baffa5f719eb2ae9729088bc867f972f53 ("ARM: OMAP2+: hwmod: Revert "ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status""); added kerneldoc; rolled in warning fix from Kevin] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod_data: Name the common irq for McBSP portsPeter Ujfalusi2012-05-081-4/+4
| | | | | | | | Use 'common' as name for the common irq number in hwmod data for the McBSP ports. The same name already in use for OMAP2430, and OMAP3. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: I2C: add flag for context restoreShubhrajyoti D2012-05-081-1/+2
| | | | | | | | | | | | | | Restore of context is not done for OMAP4. This patch adds the OMAP_I2C_FLAG_RESET_REGS_POSTIDLE in the OMAP4 hwmod data which activates the restore for OMAP4. Currently the OMAP4 does not hit device off still the driver may have support for it. Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Wamsley <paul@pwsan.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: add DEBUGSS skeletonBenoît Cousson2012-04-191-7/+52
| | | | | | | | | | Add a skeleton hwmod for the DEBUGSS and associated interconnect data. This is a basic set of data that will need further additions as further DEBUGSS information becomes available. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: add PRCM and related IP blocksPaul Walmsley2012-04-191-5/+162
| | | | | | | | | Add the PRCM, CM, PRM, and related hwmod and associated interconnect data. These IP blocks handle most of the on-chip power, reset, and clock control. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: add System Control ModulePaul Walmsley2012-04-191-4/+130
| | | | | | | Add the System Control Module hwmod and associated interconnect data. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: add the OCP-WP IP blockBenoît Cousson2012-04-191-1/+50
| | | | | | | | | Add the OCP-WP hwmod and associated interconnect data. The OCP-WP, or OCP watchpoint, can be used to collect interconnect data and transmit it via the STM port. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: add OCM RAM IP blockPaul Walmsley2012-04-191-1/+31
| | | | | | | | Add the OCM RAM IP block and interconnect data. This is an oh-chip block of SRAM connected directly to the L3 bus. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: add remaining USB-related IP blocksBenoît Cousson2012-04-191-4/+116
| | | | | | | | | | | | | | Add the OCP2SCP IP block and interconnect data. The OCP2SCP can be used in conjunction with the on-chip embedded USB PHY, associated with the OTG controller. Add the on-chip full-speed USB host controller IP block and interconnect data. Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: add some interconnect-related IP blocksPaul Walmsley2012-04-191-4/+220
| | | | | | | | | | | | | | | | | Add the SL2 interface IP block and interconnect data. The SL2 is related to the IVA-HD subsystem. Add IP block and interconnect data for the C2C ("Chip-to-chip") interconnect. This can provide a direct system interconnect link to other devices stacked on the OMAP package. Add the ELM IP block and interconnect data. The ELM can be used to locate errors in NAND flash connected to the GPMC. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: add McASPBenoît Cousson2012-04-191-1/+90
| | | | | | | | Add the McASP hwmod and associated interconnect data. The McASP is a general-purpose audio serial port. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: add the Slimbus IP blocksBenoît Cousson2012-04-191-2/+161
| | | | | | | | | | | Add the Slimbus hwmods and associated interconnect data. The Slimbus IP blocks implement a two-wire serial interface. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: add GPUPaul Walmsley2012-04-191-1/+69
| | | | | | | | Add the GPU hwmod and associated interconnect data. The GPU is a graphics accelerator. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: add EMIF1 and 2Paul Walmsley2012-04-191-2/+96
| | | | | | | | Add the EMIF1 and 2 hwmods and associated interconnect data. The EMIFs are SDRAM interface IP blocks. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: add GPMCBenoît Cousson2012-04-191-1/+66
| | | | | | | | | | Add the GPMC hwmod and associated interconnect data. The GPMC is a programmable parallel-bus memory controller. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: add HDQ/1-wirePaul Walmsley2012-04-191-1/+60
| | | | | | | | | Add the HDQ/1-wire hwmod and associated interconnect data. The HDQ/1-wire IP block is a low-speed serial interconnect. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: introduce fdif(face detect module) hwmodMing Lei2012-04-191-1/+78
| | | | | | | | | | | | | | | | | | Add hwmod data for the OMAP4 FDIF IP block. This patch also includes a change (originally from Fernando Guzman Lugo <fernando.lugo@ti.com>) to set a softreset delay for the FDIF IP block: http://www.spinics.net/lists/arm-kernel/msg161874.html Signed-off-by: Ming Lei <ming.lei@canonical.com> Acked-by: Benoît Cousson <b-cousson@ti.com> Cc: Fernando Guzman Lugo <fernando.lugo@ti.com> [paul@pwsan.com: rearranged to match script output; fixed FDIF end address to match script data; wrote trivial changelog; combined the FDIF portion of Fernando's srst_udelay patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP2+: hwmod data: remove forward declarations, reorganizePaul Walmsley2012-04-191-1975/+1903
| | | | | | | | | | | | | Reorganize the hwmod data to declare the IP blocks first and the interconnects second. This allows us to remove the forward declarations, which this patch also does. Saves some lines of source data. While here, take the opportunity to synchronize the order of the OMAP44xx hwmod data with the autogenerator output -- it's slightly different due to past mismerges -- and fix a few minor typos and whitespace problems in the files. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP2+: hwmod data: convert to link registrationPaul Walmsley2012-04-191-814/+121
| | | | | | | | | | | | | | | | Register interconnect links between IP blocks, rather than the IP blocks themselves. (The IP blocks will be registered as a side-effect of registering the links.) The objective is to reduce the number of lines of static data and facilitate the sharing of IP block data between different SoCs. These objectives come at the penalty of increased boot time due to increased computation. While here, fix a few whitespace problems and inaccurate variable names. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: uncomment some "excluded" hwmodsPaul Walmsley2012-04-191-4/+4
| | | | | | | | | | | | | Some hwmods were commented out from the OMAP4 data, under the theory that they shouldn't be added until drivers were ready. But part of the utility of the hwmod code is that it can reset and properly initialize IP blocks that have no drivers associated with them. Rather than commenting the links in the future hwmod data conversion patches, discussing this with Benoit, it seems best to simply uncomment them now. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: add OCP_USER_DSP; mark omap44xx_dsp__iva appropriatelyPaul Walmsley2012-04-191-0/+1
| | | | | | | | | | | | | | | | One of the OMAP4 links was missing OCP_USER flags, since it was only used by the DSP initiator, and we did not have an OCP_USER_DSP flag. Future patches will switch the hwmod code and data to register interfaces, rather than hwmods, and it will be mandatory for all interfaces to have at least one user bit set. This patch resolves the issue by adding OCP_USER_DSP and marking the DSP-IVA interface appropriately. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: remove bandgap hwmodPaul Walmsley2012-04-191-30/+0
| | | | | | | | | | | | | Commit 407a6888f7362cb3dabe69ea6d9dcf3c750dc56a ("OMAP4: hwmod data: Add AESS, McPDM, bandgap, counter_32k, MMC, KBD, ISS & IPU") adds a hwmod for the bandgap die temperature sensor IP block. This IP block has no interconnect port or firewall region, nor does it have an independent register space or OCP control registers. Its registers are embedded in the System Control Module (SCM) IP block. So it appears that the bandgap device should be created by the SCM driver. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP4: hwmod data: remove pseudo-hwmods associated with hardreset linesPaul Walmsley2012-04-181-98/+3
| | | | | | | | | | | | | | | | | | | | | Remove the pseudo-hwmods associated with hardreset lines from the OMAP4 data file. Future patches will convert this data to register hwmods by interfaces, rather than registering hwmods directly. The pseudo-hwmods aren't associated with any interfaces, so this will create a problem. After this change, the hwmod code will reset processor IPs at the hwmod level, rather than by individual hardreset lines. So, for example, if the IVA device driver code wishes to place one of the sequencer cores into reset, while leaving the other active, it must do so itself by calling the appropriate PRM functions. This patch will cause a change in the initialization behavior of the DSP, IVA, and IPU. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
* ARM: OMAP2+: hwmod: add softreset delay field and OMAP4 dataFernando Guzman Lugo2012-04-131-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Due to HW limitation, some IPs should not be accessed just after a softreset. Since the current hwmod sequence is accessing the sysconfig register just after the reset, it might lead to OCP bus error in that case. Add a new field in the sysconfig structure to specify a delay in usecs needed after doing a softreset. In the case of the ISS and FDIF modules, the L3 OCP port will be disconnected upon a SW reset. That issue was confirmed with HW simulation and an errata should be available soon. The HW recommendation to avoid that is to wait for 100 OCP clk cycles, before accessing the IP. Considering the worse case (OPP50), the L3 bus will run at 100 MHz, so a 1 usec delay is needed. Add an x2 margin to be safe. Acked-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Fernando Guzman Lugo <fernando.lugo@ti.com> [paul@pwsan.com: dropped FDIF change for now since the hwmod data is not yet upstream; the FDIF change will need to be added later once the FDIF data is merged] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: hwmod data: Add aliases for McBSP fclk clocksPaul Walmsley2012-04-041-0/+28
| | | | | | | | | | | | | | CLKS signal for McBSP ports can be selected from internal (PRCM) or external (ABE_CLKS pin) source. To be able to use existing code we need to create clock aliases consistent among OMAP2/3/4. Based on a patch from Péter Ujfalusi <peter.ujfalusi@ti.com>; the patch description above is his. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Péter Ujfalusi <peter.ujfalusi@ti.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
* Merge branch 'next/fixes-non-critical' into next/driversArnd Bergmann2012-03-201-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-lpc32xx/clock.c arch/arm/mach-pxa/pxa25x.c arch/arm/mach-pxa/pxa27x.c The conflicts with pxa are non-obvious, we have multiple branches adding and removing the same clock settings. According to Haojian Zhuang, removing the sa1100 rtc dummy clock is the correct fix here. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: OMAP2+: included some headers twiceDanny Kukawka2012-03-051-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | arch/arm/mach-omap2/: included some headers tiwce: - arch/arm/mach-omap2/board-ldp.c: 'linux/gpio.h' - arch/arm/mach-omap2/io.c: 'common.h' - arch/arm/mach-omap2/omap_hwmod_44xx_data.c: 'plat/i2c.h' Remove the duplicates. Signed-off-by: Danny Kukawka <danny.kukawka@bisect.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP3+: SmartReflex: use voltage domain name in device attributesShweta Gulati2012-03-051-3/+16
|/ | | | | | | | | | | | | | | | | | | | | | | To set sr ntarget values for all volt_domain, volt_table is retrieved by doing a look_up of 'vdd_name' field from omap_hwmod but voltage domain pointer does not belong to omap_hwmod and is not used anywhere else. As a part of voltage layer and SR Layer clean up volt pointer is removed from omap_hwmod and added in dev attributes of SR. The value of the field must match the voltage domain names for the binding to be effective. Tested on OMAP3630 SDP, OMAP3530 Beagleboard and OMAP4430 SDP Board. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Shweta Gulati <shweta.gulati@ti.com> Acked by: Nishanth Menon <nm@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: hwmod data: Add names for DMIC memory address spacePeter Ujfalusi2012-01-251-0/+2
| | | | | | | | | | | | | To be able to get the memory resources by name from the DMIC driver (for MPU and for DMA). Without this patch, functionality that was working in 3.2 breaks in 3.3-rc1. This patch should have gone in as part of the 3.3 merge window, but was inadvertently missed. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> [paul@pwsan.com: added commit message note] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP3+: hwmod data: Add the default clockactivity for I2CShubhrajyoti D2011-12-161-4/+5
| | | | | | | | | | | | | | | | | | | | For I2C clockactivity field is added for OMAP3 and OMAP4 that defines how the interface (OCP) and functional (system) clocks behave when the I2C module is idle. The configuration of the clock activity bit field (per TRM) is as follows: 0x0: Both clocks can be cut off 0x1: Only OCP clock must be kept active; system clock can be cut off 0x3: Both clocks must be kept active 0x2: Only system clock must be kept active; OCP clock can be cut off The patch makes 0x2(CLOCKACT_TEST_ICLK) the default for OMAP3 and OMAP4. Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP4Benoit Cousson2011-12-161-1/+207
| | | | | | | | | | | | | | | | | | | Following 2 hwmod structures are added 1. usb_host_hs The hwmod of usbhs with uhh, ehci and ohci base addresses functional clock and ehci, ohci irqs 2. usb_tll_hs hwmod of usbhs with the TLL base address and irq. Signed-off-by: Benoit Cousson <b-cousson@ti.com> [keshava_mgowda@ti.com: rebased to kernel version 3.0, added workarounds for hardware issues] Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com> Reviewed-by: Partha Basak <parthab@india.ti.com> [paul@pwsan.com: fixed multi-line comments, fixed whitespace, fixed S-o-b notes, removed spurious TLL->L3 interface] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP2PLUS: DSS: Ensure DSS works correctly if display is enabled in ↵Archit Taneja2011-11-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | bootloader Resetting DISPC when a DISPC output is enabled causes the DSS to go into an inconsistent state. Thus if the bootloader has enabled a display, the hwmod code cannot reset the DISPC module just like that, but the outputs need to be disabled first. Add function dispc_disable_outputs() which disables all active overlay manager and ensure all frame transfers are completed. Modify omap_dss_reset() to call this function and clear DSS_CONTROL, DSS_SDI_CONTROL and DSS_PLL_CONTROL so that DSS is in a clean state when the DSS2 driver starts. This resolves the hang issue(caused by a L3 error during boot) seen on the beagle board C3, which has a factory bootloader that enables display. The issue is resolved with this patch. Thanks to Tomi and Sricharan for some additional testing. Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: R, Sricharan <r.sricharan@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> [paul@pwsan.com: restructured code, removed omap_{read,write}l(), removed cpu_is_omap*() calls and converted to dev_attr] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP: HWMOD: Unify DSS resets for OMAPsTomi Valkeinen2011-11-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a custom DSS reset function used on OMAPs from OMAP2 forward. The function doesn't actually do a reset, it only waits for the reset to complete. The reason for this is that on OMAP4 there is no possibility to do a SW reset, and on OMAP2/3 doing a SW reset for dss_core resets all the other DSS modules also, thus breaking the HWMOD model where every DSS module is handled independently. This fixes the problem with DSS reset on OMAP4, caused by the fact that because there's no SW reset for dss_core on OMAP4, the HWMOD framework doesn't try to reset dss_core and thus the DSS clocks were never enabled at the same time. This causes causes the HWMOD reset to fail for dss_dispc and dss_rfbi. The common reset function will also allow us to fix another problem in the future: before doing a reset we need to disable DSS outputs, which are in some cases enabled by the bootloader, as otherwise DSS HW seems to get more or less stuck, requiring a power reset to recover. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [paul@pwsan.com: modified to build arch/arm/mach-omap2/display.o unconditionally to avoid an error when !CONFIG_OMAP2_DSS] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: HWMOD: fix DSS clock dataTomi Valkeinen2011-11-081-3/+3
| | | | | | | | | | | | | | | | The OMAP4 HWMOD data currently contains errors with DSS clocks: dss_hdmi and dss_venc have their main_clks wrong. The clocks should be dss_48mhz_clk and dss_tv_clk, respectively. These problems were temporarily fixed with the DSS patches 9ede365aa6f74428a1f69c21ca1cf21213167576 ("HACK: OMAP: DSS2: clk hack for OMAP2/3"), and df5d3ed23cf73ee0763a8963003bda9b69d9620f ("OMAP: DSS2: HDMI: fix hdmi clock name"), which can be reverted after this patch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: HWMOD: Add HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_coreTomi Valkeinen2011-11-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | DSS needs all DSS clocks to be enabled to be able to finish reset properly. Before v3.1-rc1 the omapdss driver was managing clocks and resets correctly. However, when omapdss started using runtime PM at v3.1-rc1, the responsibility for the reset moved to HWMOD framework. HWMOD framework does not currently enable all the DSS clocks when resetting the DSS hardware. This causes the HWMOD frameworks boot-time reset to fail, possibly leaving the DSS hardware in undefined state. This patch sets HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core. The flag is actually not used on OMAP4, because dss_core hardware does not have soft-reset functionality and thus the HWMOD framework never resets nor waits for the reset to finish. However, while the flag is not strictly needed currently, I think it represents the HW correctly: all the DSS clocks should be enabled after power-on to allow DSS hardware to finish its reset. A custom reset function will be added in the following patches which manages this correctly for OMAP4. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: HWMOD: remove extra clocksTomi Valkeinen2011-11-081-9/+0
| | | | | | | | | | Remove the dss_dss_clk from dss_core's opt-clocks. dss_dss_clk already defined as the dss main_clk, and thus is not needed as an opt-clock. Remove opt-clocks for dss_dispc, as dispc only uses the main_clk. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'next/timer' of git://git.linaro.org/people/arnd/arm-socLinus Torvalds2011-11-011-0/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next/timer' of git://git.linaro.org/people/arnd/arm-soc: clocksource: fixup ux500 build problems ARM: omap: use __devexit_p in dmtimer driver ARM: ux500: Reprogram timers upon resume ARM: plat-nomadik: timer: Export reset functions ARM: plat-nomadik: timer: Add support for periodic timers ARM: ux500: Move timer code to separate file ARM: ux500: add support for clocksource DBX500 PRCMU clocksource: add DBX500 PRCMU Timer support ARM: plat-nomadik: MTU sched_clock as an option ARM: OMAP: dmtimer: add error handling to export APIs ARM: OMAP: dmtimer: low-power mode support ARM: OMAP: dmtimer: skip reserved timers ARM: OMAP: dmtimer: pm_runtime support ARM: OMAP: dmtimer: switch-over to platform device driver ARM: OMAP: dmtimer: platform driver ARM: OMAP2+: dmtimer: convert to platform devices ARM: OMAP1: dmtimer: conversion to platform devices ARM: OMAP2+: dmtimer: add device names to flck nodes ARM: OMAP: Add support for dmtimer v2 ip
| * ARM: OMAP2+: dmtimer: convert to platform devicesTarun Kanti DebBarma2011-09-211-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add routines to converts dmtimers to platform devices. The device data is obtained from hwmod database of respective platform and is registered to device model after successful binding to driver. In addition, capability attribute of each of the timers is added in hwmod database. Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Thara Gopinath <thara@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Cousson, Benoit <b-cousson@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge branch 'next/cleanup' of git://git.linaro.org/people/arnd/arm-socLinus Torvalds2011-11-011-82/+0
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next/cleanup' of git://git.linaro.org/people/arnd/arm-soc: (125 commits) ARM: mach-mxs: fix machines' initializers order mmc: mxcmmc: explicitly includes mach/hardware.h arm/imx: explicitly includes mach/hardware.h in pm-imx27.c arm/imx: remove mx27_setup_weimcs() from mx27.h arm/imx: explicitly includes mach/hardware.h in mach-kzm_arm11_01.c arm/imx: remove mx31_setup_weimcs() from mx31.h ARM: tegra: devices.c should include devices.h ARM: tegra: cpu-tegra: unexport two functions ARM: tegra: cpu-tegra: sparse type fix ARM: tegra: dma: staticify some tables and functions ARM: tegra: tegra2_clocks: don't export some tables ARM: tegra: tegra_powergate_is_powered should be static ARM: tegra: tegra_rtc_read_ms should be static ARM: tegra: tegra_init_cache should be static ARM: tegra: pcie: 0 -> NULL changes ARM: tegra: pcie: include board.h ARM: tegra: pcie: don't cast __iomem pointers ARM: tegra: tegra2_clocks: 0 -> NULL changes ARM: tegra: tegra2_clocks: don't cast __iomem pointers ARM: tegra: timer: don't cast __iomem pointers ... Fix up trivial conflicts in arch/arm/mach-omap2/Makefile, arch/arm/mach-u300/{Makefile.boot,core.c} arch/arm/plat-{mxc,omap}/devices.c
| * OMAP2+: hwmod: remove OMAP_CHIP*Paul Walmsley2011-09-141-82/+0
| | | | | | | | | | | | | | | | | | | | | | | | At Tony's request, remove the OMAP_CHIP* flags from the hwmod data, and replace it instead with chip family, variant, and ES level-specific lists of hwmods to register. Thanks to Gražvydas Ignotas <notasas@gmail.com> for finding a bug in the AM3517/3505 support, and for other review comments. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Gražvydas Ignotas <notasas@gmail.com>
* | OMAP4: hwmod: enable mcpdm hwmod device.Peter Ujfalusi2011-09-221-1/+1
|/ | | | | | | | | | Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Jorge Eduardo Candelaria Signed-off-by: Margarita Olaya Cabrera Signed-off-by: Liam Girdwood <lrg@ti.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
* OMAP4: hwmod data: Add modulemode entry in omap_hwmod structureBenoit Cousson2011-07-101-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a new field to provide the mode supported by the module. The mode will control the way mandatory clocks are managed by the PRCM. 0 : Module is temporarily disabled by SW. OCP access to module are stalled. Can be used to change timing parameter of GPMC module. 1 : Module is managed automatically by HW according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any OCP access to module is always granted. Module clocks may be gated according to the clock domain state. 2 : Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. Some modules will have a modulemode initialized at 1 (HWCTRL) by default. This is the case for interconnect and simple module like GPIO, WDT, MAILBOX. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4: hwmod data: Add PRM context register offsetBenoit Cousson2011-07-101-0/+74
| | | | | | | | | | | | Add a 'context_offs' entry in the prcm.omap4 structure to all IPs when applicable. The offset will be used to retrieve the per module context lost information now available on OMAP4. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4: hwmod: Replace RSTCTRL absolute address with offset macrosBenoit Cousson2011-07-101-8/+8
| | | | | | | | | | | | | | | | | | | The RSTCTRL register was accessed using an absolute address. The usage of hardcoded macros to calculate virtual address from physical one should be avoided as much as possible. The usage of an offset will allow future improvement like migration from the current architecture code toward a module driver. Update prm_xxx accessors, move definition to the proper header file and update copyrights. Change the s16 register offset parameter to u16. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: use '_prminst_' in function names that are part of the prminst44xx.c file] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4: hwmod: Replace CLKCTRL absolute address with offset macrosBenoit Cousson2011-07-101-66/+116
| | | | | | | | | | | | | | | | | | | | The CLKCTRL register was accessed using an absolute address. The usage of hardcoded macros to calculate virtual address from physical one should be avoided as much as possible. The usage of a offset will allow future improvement like migration from the current architecture code toward a module driver. Update cm_xxx accessor, move definition to the proper header file and update copyrights. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Todd Poynor <toddpoynor@google.com> [paul@pwsan.com: renamed 'omap4_cm_' fns to 'omap4_cminst_'; removed empty fn prototype section from cm44xx.h; incorporated comments from Todd; documented some functions] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4: hwmod data: Add clock domain attributeBenoit Cousson2011-07-101-2/+83
| | | | | | | | | | | | | | | | | | | | | | | | In OMAP PRCM terminology, the clock domain is defined as a group of IPs that share some clocks and most of the time an interface clock. Every IP does belong to a clockdomain. For the moment the clock domain attribute is affected to a clock node. The issue with that approach, is that a clock might or not belong to a clock domain. Moreover during module transition, it is up to a module to handle properly the clock domain state and not to a clock node. Create a clkdm_name attribute to provide this information per hwmod. Populate this attribute for every OMAP4 hwmod entries. Future cleanup series with remove that information from the OMAP4 clock when it is relevant. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: fix the mpuss_clkdm name] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP: hwmod: fix the i2c-reset timeout during bootupAvinash.H.M2011-07-101-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | The sequence of _ocp_softreset doesn't work for i2c. The i2c module has a special sequence to reset the module. The sequence is - Disable the I2C. - Write to SOFTRESET bit. - Enable the I2C. - Poll on the RESETDONE bit. The sequence is implemented as a function and the i2c_class is updated with the correct 'reset' pointer. omap_hwmod_softreset function is implemented which triggers the softreset by writing into sysconfig register. On following this sequence, i2c module resets properly and timeouts are not seen. Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Avinash.H.M <avinashhm@ti.com> [paul@pwsan.com: combined this patch with a patch to remove HWMOD_INIT_NO_RESET from the 44xx hwmod flags; change register offset conditional code to use the IP block revision; minor code cleanup] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* I2C: OMAP2+: add correct functionality flags to all omap2plus i2c dev_attrAndy Green2011-07-101-0/+9
| | | | | | | | | | | | | This adds the new functionality flags for omap i2c unit to all OMAP2 hwmod definitions Cc: patches@linaro.org Cc: Ben Dooks <ben-linux@fluff.org> Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andy Green <andy.green@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* I2C: OMAP2+: Tag all OMAP2+ hwmod defintions with I2C IP revisionAndy Green2011-07-101-0/+1
| | | | | | | | | | | | | | | | | Since we cannot trust (or even reliably find) the OMAP I2C peripheral unit's own revision register, we must inform the OMAP i2c driver of which IP version it is running on. We do this by tagging the omap_hwmod_class for i2c on all the OMAP2+ platform / cpu specific hwmod init and passing it up to the driver (next patches). Cc: patches@linaro.org Cc: Ben Dooks <ben-linux@fluff.org> Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andy Green <andy.green@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* I2C: OMAP2+: Set hwmod flags to only allow 16-bit accesses to i2cAndy Green2011-07-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Peter Maydell noticed when running under QEMU he was getting errors reporting 32-bit access to I2C peripheral unit registers that are documented to be 8 or 16-bit only[1][2] The I2C driver is blameless as it wraps its accesses in a function using __raw_writew and __raw_readw, it turned out it is the hwmod stuff. However the hwmod code already has a flag to force a perhipheral unit to only be accessed using 16-bit operations. This patch applies the 16-bit only flag to the 2430, OMAP3xxx and OMAP44xx hwmod structs. 2420 was already correctly marked up as 16-bit. The 2430 change will need testing by TI as arranged in the comments to the previous patch version. When the 16-bit flag is or-ed with other flags, it is placed first as requested in comments. [1] OMAP4430 Technical reference manual section 23.1.6.2 [2] OMAP3530 Techincal reference manual section 18.6 Cc: patches@linaro.org Cc: Ben Dooks <ben-linux@fluff.org> Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andy Green <andy.green@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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