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* Merge tag 'davinci-for-v3.16/edma' of ↵Olof Johansson2014-05-261-101/+96
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers Merge "DaVinci EDMA clean-up for v3.16" from Sekhar Nori: This series makes edma use configuration information available within the IP instead of reading it from platform data or DT. Some other useful clean-ups are included too. * tag 'davinci-for-v3.16/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: (34 commits) ARM: edma: Remove redundant/unused parameters from edma_soc_info ARM: davinci: Remove redundant/unused parameters for edma ARM: dts: am4372: Remove obsolete properties from edma node ARM: dts: am33xx: Remove obsolete properties from edma node dt/bindings: ti,edma: Remove redundant properties from documentation ARM: edma: Get IP configuration from HW (number of channels, tc, etc) ARM: edma: Save number of regions from pdata to struct edma ARM: edma: Remove num_cc member from struct edma ARM: edma: Remove queue_tc_mapping data from edma_soc_info ARM: davinci: Remove eDMA3 queue_tc_mapping data from edma_soc_info ARM: edma: Do not change TC -> Queue mapping, leave it to default. ARM: edma: Take the number of tc from edma_soc_info (pdata) ARM: edma: No need to clean the pdata in edma_of_parse_dt() ARM: edma: Clean up and simplify the code around irq request dmaengine: edma: update DMA memcpy to use new param element dmaengine: edma: Document variables used for residue accounting dmaengine: edma: Provide granular accounting dmaengine: edma: Make reading the position of active channels work dmaengine: edma: Store transfer data in edma_desc and edma_pset dmaengine: edma: Create private pset struct ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: edma: Get IP configuration from HW (number of channels, tc, etc)Peter Ujfalusi2014-05-221-42/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From CCCFG register of eDMA3 we can get all the needed information for the driver about the IP: Number of channels: NUM_DMACH Number of regions: NUM_REGN Number of slots (PaRAM sets): NUM_PAENTRY Number of TC/EQ: NUM_EVQUE In case when booted with DT or the queue_priority_mapping is not provided set up a default priority map. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| * ARM: edma: Save number of regions from pdata to struct edmaPeter Ujfalusi2014-05-221-1/+2
| | | | | | | | | | | | | | | | To be consistent in the code that we take parameters from edma_cc[j] struct and not randomly from info[j] as well. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| * ARM: edma: Remove num_cc member from struct edmaPeter Ujfalusi2014-05-221-4/+0
| | | | | | | | | | | | | | | | The struct edma is allocated per CC bases so the member num_cc does not make any sense. One CC is one CC, it does not have sub CCs. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| * ARM: edma: Do not change TC -> Queue mapping, leave it to default.Peter Ujfalusi2014-05-221-27/+1
| | | | | | | | | | | | | | | | | | | | There is no need to change the default TC -> Queue mapping. By default the mapping is: TC0 -> Q0, TC1 -> Q1, etc. Changing this has no benefits at all and all the board files are just setting the same mapping back to the HW. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| * ARM: edma: Take the number of tc from edma_soc_info (pdata)Peter Ujfalusi2014-05-221-3/+2
| | | | | | | | | | | | | | | | | | | | Instead of saving the for loop length, take the num_tc value from the pdata. In case of DT boot set the n_tc to 3 as it is hardwired in edma_of_parse_dt() This is a temporary state since upcoming patch(es) will change how we are dealing with these parameters. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| * ARM: edma: No need to clean the pdata in edma_of_parse_dt()Peter Ujfalusi2014-05-221-2/+0
| | | | | | | | | | | | | | | | The pdata has been just allocated with devm_kzalloc() in edma_setup_info_from_dt() and passed to this function. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| * ARM: edma: Clean up and simplify the code around irq requestPeter Ujfalusi2014-05-221-14/+12
| | | | | | | | | | | | | | | | | | | | Get the two interrupt line number at the same time by merging the two instance of if(node){}else{} places. replace the &pdev->dev with the already existing dev which makes it possible to collapse lines with devm_request_irq() Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| * dmaengine: edma: Make reading the position of active channels workThomas Gleixner2014-04-301-15/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As Joel pointed out, edma_read_position() uses memcpy_fromio() to read the parameter ram. That's not synchronized with the internal update as it does a byte by byte copy. We need to do a 32bit read to get a consistent value. Further reading destination and source is pointless. In DEV_TO_MEM transfers we are only interested in the destination, in MEM_TO_DEV we care about the source. In MEM_TO_MEM it really does not matter which one you read. Simple solution: Remove the pointers, select dest/source via a bool and return the read value. Remove the export of this function while at it. The only potential user is the dmaengine and that's always builtin. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: edma: Set DMA_CYCLIC capability flagPeter Ujfalusi2014-04-221-0/+1
| | | | | | | | | | | | | | | | | | Indicate that the edma dmaengine driver has support for cyclic mode. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Joel Fernandes <joelf@ti.com> Reviewed-and-Tested-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * arm: common: edma: Save the number of event queues/TCsPeter Ujfalusi2014-04-221-0/+3
| | | | | | | | | | | | | | | | | | For later use save the number of queues available for the CC. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Joel Fernandes <joelf@ti.com> Reviewed-and-Tested-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | ARM: common: edma: Fix xbar mappingThomas Gleixner2014-04-291-33/+15
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is another great example of trainwreck engineering: commit 2646a0e529 (ARM: edma: Add EDMA crossbar event mux support) added support for using EDMA on peripherals which have no direct EDMA event mapping. The code compiles and does not explode in your face, but that's it. 1) Reading an u16 array from an u32 device tree array simply does not work. Even if the function is named "edma_of_read_u32_to_s16_array". It merily calls of_property_read_u16_array. So the resulting 16bit array will have every other entry = 0. 2) The DT entry for the xbar registers related to xbar has length 0x10 instead of the real length: 0xfd0 - 0xf90 = 0x40. Not a real problem as it does not cross a page boundary, but wrong nevertheless. 3) But none of this matters as the mapping never happens: After reading nonsense edma_of_read_u32_to_s16_array() invalidates the first array entry pair, so nobody can ever notice the braindamage by immediate explosion. Seems the QA criteria for this code was solely not to explode when someone adds edma-xbar-event-map entries to the DT. Goal achieved, congratulations! Not really helpful if someone wants to use edma on a device which requires a xbar mapping. Fix the issues by: - annotating the device tree entry with "/bits/ 16" as documented in the of_property_read_u16_array kernel doc - make the size of the xbar register mapping correct - invalidating the end of the array and not the start This convoluted mess wants to be completely rewritten as there is no point to keep the xbar_chan array memory and the iomapping of the xbar regs around forever. Marking the xbar mapped channels as used should be done right there. But that's a different issue and this patch is small enough to make it work and allows a simple backport for stable. Cc: stable@vger.kernel.org # v3.12+ Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* dmanengine: fix edma driver to not define DMA_COMPLETEVinod Koul2013-10-301-2/+2
| | | | | | | | | edma header defines DMA_COMPLETE, this causes issues as commit adfedd9a32e4 move DMA_SUCCESS to DMA_COMPLETE. edma should properly namespace its defines and needs a future fix Reported-by: Olof Johansson <olof@lixom.net> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* ARM: edma: Fix clearing of unused list for DT DMA resourcesJoel Fernandes2013-09-301-7/+31
| | | | | | | | | | | | | | | | | | | | | | | | HWMOD removal for MMC is breaking edma_start as the events are being manually triggered due to unused channel list not being clear. The above issue is fixed by reading the "dmas" property from the DT node if it exists and clearing the bits in the unused channel list if the dma controller used by any device is EDMA. For this purpose we use the of_* helpers to parse the arguments in the dmas phandle list. Also introduced is a minor clean up of a checkpatch error in old code. Reviewed-by: Sekhar Nori <nsekhar@ti.com> Reported-by: Balaji T K <balajitk@ti.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Olof Johansson <olof@lixom.net> Cc: Nishanth Menon <nm@ti.com> Cc: Pantel Antoniou <panto@antoniou-consulting.com> Cc: Jason Kridner <jkridner@beagleboard.org> Cc: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: edma: Add function to manually trigger an EDMA channelJoel Fernandes2013-09-041-0/+17
| | | | | | | | | | Manual trigger for events missed as a result of splitting a scatter gather list and DMA'ing it in batches. Add a helper function to trigger a channel incase any such events are missed. Signed-off-by: Joel Fernandes <joelf@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* ARM: edma: remove duplicated include from edma.cWei Yongjun2013-07-161-1/+0
| | | | | | | Remove duplicated include. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* ARM: edma: Add EDMA crossbar event mux supportMatt Porter2013-06-241-0/+78
| | | | | | | | | | | | | | | | | | | | | | EDMA supports a cross bar which provides ability to mux additional events into physical channels present in the channel controller. This is required when the number of events present in the system are more than number of available physical channels. Changes by Joel: * Split EDMA xbar support out of original EDMA DT parsing patch to keep it easier for review. * Rewrite shift and offset calculation. Suggested-by: Sekhar Nori <nsekhar@ti.com> Suggested by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> [nsekhar@ti.com: fix checkpatch errors and a minor coding improvement] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* ARM: edma: Add DT and runtime PM support to the private EDMA APIMatt Porter2013-06-241-13/+173
| | | | | | | | | | | | | | | | | | | | | | Adds support for parsing the TI EDMA DT data into the required EDMA private API platform data. Enables runtime PM support to initialize the EDMA hwmod. Enables build on OMAP. Changes by Joel: * Setup default one-to-one mapping for queue_priority and queue_tc mapping as discussed in [1]. * Split out xbar stuff to separate patch. [1] * Dropped unused DT helper to convert to array * Fixed dangling pointer issue with Sekhar's changes [1] https://patchwork.kernel.org/patch/2226761/ Signed-off-by: Matt Porter <mporter@ti.com> [nsekhar@ti.com: fix checkpatch errors, build breakages. Introduce edma_setup_info_from_dt() as part of that effort] Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* ARM: edma: Convert to devm_* apiLad, Prabhakar2013-06-181-45/+20
| | | | | | | | | | | | Use devm_ioremap_resource instead of reques_mem_region()/ioremap(), devm_request_irq() instead of request_irq() and kzalloc() calls to devm_kzalloc(). This ensures more consistent error values and simplifies error paths. Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> [nsekhar@ti.com: add missing err.h include] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* ARM: edma: remove unused transfer controller handlersMatt Porter2013-06-181-37/+0
| | | | | | | | | Fix build on OMAP, the irqs are undefined on AM33xx. These error interrupt handlers were hardcoded as disabled so since they are unused code, simply remove them. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* ARM: davinci: move private EDMA API to arm/commonMatt Porter2013-06-181-0/+1591
Move mach-davinci/dma.c to common/edma.c so it can be used by OMAP (specifically AM33xx) as well. Signed-off-by: Matt Porter <mporter@ti.com> Acked-by: Chris Ball <cjb@laptop.org> # davinci_mmc.c Acked-by: Mark Brown <broonie@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> [nsekhar@ti.com: dropped davinci sffsdr changes] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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